Patent Assignment
Reel/Frame 008826/0841
Assignment of Assignor's Interest
Recorded: 1997-09-19
Pages: 3
Assignor
GHEEWALA, TUSHAR R.
Executed: 1997-09-12
Assignee
IN-CHIP SYSTEMS, INC.
501 CASTANO CORTE, LOS ALTOS, CALIFORNIA, 94022
Covered Property
(1)
Power and Signal Routing Technique for Gate Array Design
Patent:
6,091,090 →
Application:
08/933,552 →
Related Assignments
(3)
Other recorded transfers of the patent in this record — the chain of ownership.
Security Agreement
May 24, 2002
From: IN-CHIP SYSTEMS, INC.
To: GHEEWALA, TUSHAR
Reel/Frame 012735/0281 →
Assignment of Assignor's Interest
Nov 14, 2002
From: IN-CHIP SYSTEMS, INC.
To: VIRAGE LOGIC CORPORATION
Reel/Frame 013484/0228 →
Assignment of Assignor's Interest
Oct 8, 2010
From: VIRAGE LOGIC CORPORATION; VL C.V.; ARC CORES LIMITED; ARC INTERNATIONAL I.P., INC.
To: SYNOPSYS, INC.
Reel/Frame 025105/0907 →