IP Library › Assignment 009512/0354
Patent Assignment
Reel/Frame 009512/0354

Assignment of Assignor's Interest

Recorded: 1998-10-06 Pages: 3
Assignors
TSENG, PING-SHENG
Executed: 1998-08-31
LIN, SHARON SHEAU-PYNG
Executed: 1998-08-31
SHEN, QUINCY KUN-HSU
Executed: 1998-08-31
Assignee
AXIS SYSTEMS, INC.
209 JAVA DRIVE, SUNNYVALE, CALIFORNIA, 94089
Covered Property (1)
Timing-Insensitive Glitch-Free Logic System and Method
Patent: 6,321,366 →
Application: 09/144,222 →
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Merger Mar 21, 2005
From: AXIS SYSTEMS, INC.
To: VERSITY DESIGN, INC.
Reel/Frame 015931/0096 →
Assignment of Assignor's Interest Oct 18, 2013
From: VERISITY DESIGN, INC.
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 031430/0779 →