IP Library Assignment 015931/0096
Patent Assignment
Reel/Frame 015931/0096

Merger

Recorded: 2005-03-21 Pages: 4
Assignor
AXIS SYSTEMS, INC.
Executed: 2004-04-01
Assignee
VERSITY DESIGN, INC.
2041 LANDINGS DRIVE, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Property (1)
Timing-Insensitive Glitch-Free Logic System and Method
Patent: 6,321,366 →
Application: 09/144,222 →
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Oct 6, 1998
From: TSENG, PING-SHENG; LIN, SHARON SHEAU-PYNG; SHEN, QUINCY KUN-HSU
To: AXIS SYSTEMS, INC.
Reel/Frame 009512/0354 →
Assignment of Assignor's Interest Oct 18, 2013
From: VERISITY DESIGN, INC.
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 031430/0779 →