IP Library Assignment 012359/0633
Patent Assignment
Reel/Frame 012359/0633

Assignment of Assignor's Interest

Recorded: 2001-12-07 Pages: 2
Assignors
NISHIYAMA, MASAHIKO
Executed: 2001-11-12
MITSUMOTO, KINYA
Executed: 2001-11-13
AGARI, TAKESHI
Executed: 2001-11-13
Assignee
HITACHI, LTD.
6, KANDA SURUGADAI 4-CHOME, CHIYODA-KU, TOKYO, JAPAN
Covered Property (1)
Semiconductor Memory Device Having a Double Data Rate (Ddr) Mode and Utilizing a Plurality of Comparison Circuits to Prevent Errors Due to a Late Write Function
Patent: 6,725,325 →
Application: 10/005,361 →
Publication: US 2002/0071332
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Sep 26, 2003
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORPORATION
Reel/Frame 014569/0585 →
Merger/Change of Name Aug 31, 2011
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 026837/0505 →
Change of Address Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →