IP Library Assignment 012456/0588
Patent Assignment
Reel/Frame 012456/0588

Assignment of Assignor's Interest

Recorded: 2002-01-09 Pages: 3
Assignors
HEIN, THOMAS
Executed: 2001-02-06
MARX, THILO
Executed: 2001-02-06
HEYNE, PATRICK
Executed: 2001-02-07
PARTSCH, TORSTEN
Executed: 2001-05-10
Assignee
INFINEON TECHNOLOGIES AG
PATENTABTEILUNG, ST.-MARTIN-STRASSE 53, MUENCHEN, 81541, GERMANY
Covered Property (1)
Circuit configuration for generating an output clock signal with optimized signal generation time
Patent: 6,366,527 →
Application: 09/773,220 →
Publication: US 2001/0033523
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest Sep 3, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036539/0196 →