Patent Assignment
Reel/Frame 012506/0534
Assignment of Assignor's Interest
Recorded: 2001-12-31
Pages: 24
Assignor
LUCENT TECHNOLOGIES INC.
Executed: 2001-01-31
Assignee
AGERE SYSTEMS GUARDIAN CORP.
9333 S. JOHN YOUNG PARKWAY, ORLANDO, FLORIDA, 32819
Covered Properties
(34)
Multiple Voltage Supplies for Field Programmable Gate Arrays and the Like
Patent:
5,239,510 →
Application:
07/797,648 →
Low-Skew Signal Routing in a Programmable Array
Patent:
5,384,497 →
Application:
07/971,501 →
Fpga with Distributed Switch Matrix
Patent:
5,396,126 →
Application:
08/019,963 →
Field Programmable Gate Array with Direct Input/Output Connection
Patent:
5,311,080 →
Application:
08/037,766 →
Fpga Having Pfu with Programmable Output Driver Inputs
Patent:
5,381,058 →
Application:
08/065,823 →
Programmable Function Unit with Programmable Fast Ripple Logic
Patent:
5,386,156 →
Application:
08/113,154 →
Apparatus and Method to Improve Programming Speed of Field Programmable Gate Arrays
Patent:
5,394,031 →
Application:
08/163,952 →
Field Programmable Gate Array Using Look-Uptables, Multiplexers and Decoders
Patent:
5,442,306 →
Application:
08/304,013 →
System for Synthesizing Field Programmable Gate Array Implementations from High Level Circuit Descriptions
Patent:
5,594,657 →
Application:
08/473,620 →
Method and Apparatus for Converting Field-Programmable Gate Array Implementations into Mas-Programmable Logic Cell Implementations
Patent:
5,526,278 →
Application:
08/492,604 →
Programmable Function Unit as Parallel Multiplier Cell
Patent:
5,570,039 →
Application:
08/507,893 →
Field Programmable Gate Array with Multi-Port Ram
Patent:
5,559,450 →
Application:
08/507,957 →
Low-Skew Signal Routing in a Programmable Array
Patent:
5,528,170 →
Application:
08/535,362 →
Field Programmable Gate Array with Write-Port Enabled Memory
Patent:
5,623,217 →
Application:
08/606,702 →
Configuration Pin Emulation Circuit for a Field Programmable Gate Array
Patent:
5,862,365 →
Application:
08/710,445 →
Method for Testing Field Programmable Gate Arrays
Patent:
5,991,907 →
Application:
08/729,117 →
Fpga-Based Processor
Patent:
5,892,962 →
Application:
08/748,041 →
Timed Circuit Simulation in Hardware Using Fpga's
Patent:
6,028,993 →
Application:
08/781,882 →
Fpga Having Predictable Open-Drain Drive Mode
Patent:
6,028,447 →
Application:
08/899,428 →
Hybrid Programmable Gate Arrays
Patent:
6,020,755 →
Application:
08/938,550 →
Programmable Clock Manager for a Programmable Logic Device That Can Generate at Least Two Different Output Clocks
Patent:
6,028,463 →
Application:
08/949,992 →
Field Programmable Gate Array Having a Dedicated Processor Interface
Patent:
6,216,191 →
Application:
08/950,444 →
Bi-Directional Buffers and Supplemental Logic and Interconnect Cells for Programmable Logic Devices
Patent:
5,986,471 →
Application:
08/950,446 →
Programmable Clock Manager for a Programmable Logic Device That Can Be Programmed Without Reconfiguring the Device
Patent:
6,060,902 →
Application:
08/950,448 →
Programmable Logic Device with Logic Cells Having a Flexible Input Structure
Patent:
6,049,224 →
Application:
08/950,624 →
Programmable Clock Manager for a Programmable Logic Device That Can Implement Delay-Locked Loop Functions
Patent:
6,043,677 →
Application:
08/951,128 →
Method for Testing Field Programmable Gate Arrays
Patent:
6,003,150 →
Application:
08/974,799 →
Virtual Logic System for Reconfigurable Hardware
Patent:
6,034,538 →
Application:
09/010,000 →
Global Signal Distribution with Reduced Routing Tracks in an Fpga
Patent:
6,064,225 →
Application:
09/045,128 →
Method of Testing and Diagnosing Field Programmable Gate Arrays
Patent:
6,108,806 →
Application:
09/059,552 →
Non-Volatile Memory Element for Programmable Logic Applications and Operational Methods Therefor
Patent:
6,002,610 →
Application:
09/069,768 →
Method and Apparatus for Testing Field Programmable Gate Arrays
Patent:
6,202,182 →
Application:
09/109,123 →
Signaling Voltage Range Discriminator
Patent:
6,124,732 →
Application:
09/115,683 →
Method for in-System Programming of Serially Configured Eeproms Using a Jtag Interface of a Field Programmable Gate Array
Patent:
6,137,738 →
Application:
09/452,017 →
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 17, 1996
From: MODO, RONALD T.; POWELL, GARY P.; ROBERTSON, HOLLIS G.; SMITH, WILLIAM H. III
To: LUCENT TECHNOLOGIES, INC.
Reel/Frame 008176/0615 →
Assignment of Assignor's Interest
Oct 3, 1996
From: AT&T CORP.
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 008196/0181 →
Assignment of Assignor's Interest
Oct 31, 1996
From: AT&T CORP.
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 008179/0675 →
Assignment of Assignor's Interest
Nov 15, 2004
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS INC.
Reel/Frame 015980/0344 →
Assignment of Assignor's Interest
Jul 21, 2009
From: POWELL, GARY P.
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 022980/0421 →
Assignment of Assignor's Interest
Jul 21, 2009
From: BRITTON, BARRY K.; HILL, DWIGHT D.; OSWALD, WILLIAM A.
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 022980/0390 →
Security Interest
Mar 17, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035220/0048 →
Security Interest
Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035225/0352 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →