Patent Assignment
Reel/Frame 013227/0149
Assignment of Assignor's Interest
Recorded: 2002-11-05
Pages: 5
Assignor
IN-CHIP SYSTEMS, INC.
Executed: 2002-10-25
Assignee
VIRAGE LOGIC CORPORATION
47100 BAYSIDE PARKWAY, FREMONT, CALIFORNIA, 94538
Covered Property
(1)
Gate Array Architecture Using Elevated Metal Levels for Customization
Patent:
6,617,621 →
Application:
09/588,802 →
Related Assignments
(3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 5, 2000
From: GHEEWALA, TUSHAR R.; BREID, DUANE G.; SHERLEKAR, DEEPAK D.; COLWELL, MICHAEL J.
To: IN-CHIP SYSTEMS, INC.
Reel/Frame 011229/0040 →
Security Agreement
May 24, 2002
From: IN-CHIP SYSTEMS, INC.
To: GHEEWALA, TUSHAR
Reel/Frame 012735/0281 →
Assignment of Assignor's Interest
Oct 8, 2010
From: VIRAGE LOGIC CORPORATION; VL C.V.; ARC CORES LIMITED; ARC INTERNATIONAL I.P., INC.
To: SYNOPSYS, INC.
Reel/Frame 025105/0907 →