Patent Assignment
Reel/Frame 013357/0226
Assignment of Assignor's Interest
Recorded: 2002-10-03
Pages: 2
Assignors
SUZUKI, KENJI
Executed: 2002-09-13
OSAJIMA, TORU
Executed: 2002-09-13
TAJIMA, SHOGO
Executed: 2002-09-13
SATOH, SHIGENOBU
Executed: 2002-09-13
Assignee
FUJITSU LIMITED
1-1, KAMIKODANAKA, 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN
Covered Property
(1)
Integrated Logic Circuit and Hierarchical Design Method Thereof
Related Assignments
(3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
Change of Name
Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
Assignment of Assignor's Interest
Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035507/0923 →