IP Library Assignment 014557/0982
Patent Assignment
Reel/Frame 014557/0982

Assignment of Assignor's Interest

Recorded: 2003-09-26 Pages: 3
Assignor
HITACHI, LTD.
Executed: 2003-09-12
Assignee
RENESAS TECHNOLOGY CORPORATION
4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO, JAPAN
Covered Properties (3)
Data Processor Capable of Executing an Instruction That Makes a Cache Memory Inefective
Patent: 6,779,102 →
Application: 09/886,267 →
Publication: US 2001/0032296
Single-Chip Microcomputer with Integral Clock Generating Unit Providing Clock Signals to Cpu, Internal Circuit Modules and Synchronously Controlling External Dynamic Memory
Patent: 6,748,507 →
Application: 10/172,290 →
Publication: US 2003/0046514
Single-Chip Microcomputer with Hierarchical Internal Bus Structure Having Data and Address Signal Lines Coupling Cpu with Other Processing Elements
Patent: 6,735,683 →
Application: 10/264,618 →
Publication: US 2003/0233527
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger and Change of Name Jan 10, 2011
From: RENESAS TECHNOLOGY CORP
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025632/0175 →