Patent Assignment
Reel/Frame 015698/0657
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2004-05-07
Received: 2004-05-14
Pages: 189
Assignor
MOTOROLA, INC.
Executed: 2004-04-04
Assignee
FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TX, 78735, UNITED STATES
Covered Applications
(100)
BODY-TIED SILICON ON INSULATOR SEMICONDUCTOR DEVICE AND METHOD THEREFOR
App. No. 10/462,178
→
MEHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH AN AIR GAP FORMED USING A PHOTOSENSITIVE MATERIAL
App. No. 10/445,561
→
MAGNETOELECTRONICS INFORMATION DEVICE HAVING A COMPOUND MAGNETIC FREE LAYER
App. No. 10/437,831
→
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING SAME
App. No. 10/417,992
→
INTEGRATED CIRCUIT DIE I/O CELLS
App. No. 10/409,766
→
PLATED METAL TRANSISTOR GATE AND METHOD OF FORMATION
App. No. 10/403,967
→
MAGNETIC MEMORY AND METHOD OF BI-DIRECTIONAL WRITE CURRENT PROGRAMMING
App. No. 10/401,195
→
MULTI-BIT NON-VOLATILE MEMORY DEVICE AND METHOD THEREFOR
App. No. 10/393,065
→
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING SAME
App. No. 10/389,401
→
DIGITAL TUNING SCHEME FOR CONTINUOUS-TIME SIGMA DELTA MODULATION
App. No. 10/358,055
→
DIGITAL-TO-ANALOG-CONVERTER
App. No. 10/351,724
→
DIELECTRIC BETWEEN METAL STRUCTURES AND METHOD THEREFOR
App. No. 10/350,852
→
MRAM ARCHITECTURE WITH A GROUNDED WRITE BIT LINE AND ELECTRICALLY ISOLATED READ BIT LINE
App. No. 10/346,256
→
VERTICAL MOSFET WITH ASYMMETRIC GATE STRUCTURE
App. No. 10/324,787
→
CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH DISCRETE TIME COMMON-MODE FEEDBACK
App. No. 10/324,684
→
CONTROLLED BIAS CURRENT BUFFER AND METHOD THEREOF
App. No. 10/301,992
→
METHOD OF MANUFACTURING RETICLES USING SUBRESOLUTION TEST PATTERNS
App. No. 10/284,836
→
SENSE AMPLIFIER BIAS CIRCUIT FOR A MEMORY HAVING AT LEAST TWO DISTINCT RESISTANCE STATES
App. No. 10/283,622
→
OPTICAL SENSOR PACKAGE
App. No. 10/282,537
→
CROSS COUPLED CASCODE VOLTAGE CONTROLLED OSCILLATOR
App. No. 10/281,591
→
BAND SWITCHABLE VOLTAGE CONTROLLED OSCILLATOR WITH SUBSTANTIALLY CONSTANT TUNING RANGE
App. No. 10/271,828
→
NON-VOLATILE MEMORY DEVICE HAVING AN ANTI-PUNCH THROUGH (APT) REGION
App. No. 10/267,199
→
COFIREABLE DIELECTRIC COMPOSITION
App. No. 10/256,931
→
SEMICONDUCTOR COMPONENT AND METHOD OF OPERATING SAME
App. No. 10/256,820
→
METHOD AND CIRCUITRY FOR IDENTIFYING WEAK BITS IN AN MRAM
App. No. 10/255,303
→
MULTI-STRAND SUBSTRATE FOR BALL-GRID ARRAY ASSEMBLIES AND METHOD
App. No. 10/255,257
→
INTEGRATION OF MONOCRYSTALLINE OXIDE DEVICES WITH FULLY DEPLETED CMOS ON NON-SILICON SUBSTRATES
App. No. 10/255,881
→
MULTI-BIT CONTINUOUS TIME SIGMA-DELTA ADC
App. No. 10/244,317
→
METHOD AND SYSTEM FOR DETERMINING A THICKNESS OF A LAYER
App. No. 10/243,460
→
ELECTRON OPTICS FOR MULTI-BEAM ELECTRON BEAM LITHOGRAPHY TOOL
App. No. 10/243,585
→
ACTIVE CURRENT BIAS NETWORK FOR COMPENSATING HOT-CARRIER INJECTION INDUCED BIAS DRIFT
App. No. 10/241,081
→
SEMICONDUCTOR DEVICE EXHIBITING ENHANCED PATTERN RECOGNITION WHEN ILLUMINATED IN A MACHINE VISION SYSTEM
App. No. 10/241,017
→
WAFER COATING AND SINGULATION METHOD
App. No. 10/241,265
→
WAFER CARRIER TRANSPORT SYSTEM FOR TOOL BAYS
App. No. 10/232,158
→
DATA STORAGE SYSTEM UTILIZING A NON-VOLATILE IC BASED MEMORY FOR REDUCTION OF DATA RETRIEVAL TIME
App. No. 10/230,785
→
MAGNETIC RANDOM ACCESS MEMORY HAVING A VERTICAL WRITE LINE
App. No. 10/228,684
→
DIFFERENTIAL SIGMA-DELTA DAC WITH DYNAMIC SPECTRAL SHAPING
App. No. 10/228,580
→
ELECTROSTATIC DISCHARGE PROTECTION CIRCUITRY AND METHOD OF OPERATION
App. No. 10/216,336
→
OPEN LOOP INDUCTOR CURRENT CONTROL SYSTEM AND METHOD
App. No. 10/215,582
→
HYBRID STRUCTURE FOR DISTRIBUTED POWER AMPLIFIERS
App. No. 10/211,825
→
CONDUCTIVE PASTE AND SEMICONDUCTOR COMPONENT HAVING CONDUCTIVE BUMPS MADE FROM THE CONDUCTIVE PASTE
App. No. 10/211,631
→
MAGNETORESISTANCE RANDOM ACCESS MEMORY
App. No. 10/209,156
→
BROAD BAND IMPEDANCE MATCHING DEVICE WITH COUPLED TRANSMISSION LINES
App. No. 10/208,961
→
METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE IN A SEMICONDUCTOE LAYER
App. No. 10/206,475
→
METHOD OF DECAPSULATING A PACKAGED COPPER-TECHNOLOGY INTEGRATED CIRUCIT
App. No. 10/205,865
→
MULTI-BIT NON-VOLATILE MEMORY CELL AND METHOD THEREFOR
App. No. 10/202,697
→
VARIABLE LENGTH DECODER
App. No. 10/196,532
→
BIPOLAR DIFFERENTIAL AMPLIFIER
App. No. 10/197,145
→
ENHANCED PROBE FOR GATHERING DATA FROM SEMICONDUCTOR DEVICES
App. No. 10/187,526
→
SENSE AMPLIFIER INCORPORATING A SYMMETRIC MIDPOINT REFERENCE
App. No. 10/185,224
→
MEMORY ARCHITECTURE WITH WRITE CIRCUITRY AND METHOD THEREFOR
App. No. 10/185,888
→
THREE INPUT SENSE AMPLIFIER AND METHOD OF OPERATION
App. No. 10/186,363
→
BALANCED LOAD MEMORY AND METHOD OF OPERATION
App. No. 10/184,720
→
MEMORY HAVING WRITE CURRENT RAMP RATE CONTROL
App. No. 10/185,075
→
MEMORY HAVING A PRECHARGE CIRCUIT AND METHOD THEREFOR
App. No. 10/185,488
→
SENSE AMPLIFIER FOR A MEMORY HAVING AT LEAST TWO DISTINCT RESISTANCE STATES
App. No. 10/184,784
→
CIRCUIT AND METHOD OF WRITING A TOGGLE MEMORY
App. No. 10/186,141
→
METHOD AND APPARATUS FOR MONITORING A POLISHING CONDITION OF A SURFACE OF A WAFER IN A POLISHING PROCESS
App. No. 10/180,740
→
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
App. No. 10/175,637
→
TAPERED CONSTANT "R" NETWORK FOR USE IN DISTRIBUTED AMPLIFIERS
App. No. 10/174,238
→
MAGNETORESISTIVE RANDOM ACCESS MEMORY WITH REDUCED SWITCHING FIELD
App. No. 10/173,907
→
METHOD AND APPARATUS FOR SOFT DEFECT DETECTION IN A MEMORY
App. No. 10/173,229
→
SYSTEM AND METHOD FOR REGULATING A POWER SYSTEM WITH FEEDBACK USING CURRENT SENSING
App. No. 10/155,316
→
DUAL METAL GATE TRANSISTORS FOR CMOS PROCESS
App. No. 10/151,371
→
FILTER APPARATUS AND METHOD THEREFOR
App. No. 10/142,682
→
FRONT ILLUMINATOR FOR A LIQUID CRYSTAL DISPLAY AND METHOD OF MAKING SAME
App. No. 10/142,037
→
MRAM ARCHITECTURE AND SYSTEM
App. No. 10/141,161
→
DIGITAL-TO- ANALOG CONVERSION WITH CURRENT PATH EXCHANGE DURING CLOCK PHASES
App. No. 10/135,782
→
SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER AND METHOD
App. No. 10/134,300
→
SEMICONDUCTOR DEVICE AND PROCESS FOR GENERATING AN ETCH PATTERN
App. No. 10/133,061
→
METHOD FOR CREATING A CHARACTERIZED DIGITAL LIBRARY FOR A DIGITAL CIRCUIT DESIGN
App. No. 10/128,802
→
MULTILAYER INTERGRATED CIRCUIT STRUCTURE WITH REDUCED MAGNETIC COUPLING
App. No. 10/128,043
→
METHOD FOR FORMING SERRATED CONTACT OPENING IN THE SEMICONDUCTOR DEVICE
App. No. 10/126,795
→
METHOD OF HANDLING A SILICON WAFER
App. No. 10/126,372
→
SEMICONDUCTOR DEVICE AND METHOD FOR PROTECTING SUCH DEVICE FROM A REVERSED DRAIN VOLTAGE
App. No. 10/126,562
→
LINEAR ENVELOPE TRACKING RF POWER AMPLIFIER WITH ADAPTIVE ANALOG SIGNAL PROCESSING
App. No. 10/123,271
→
BROAD BAND IMPEDANCE MATCHING DEVICE WITH REDUCED LINE WIDTH
App. No. 10/120,170
→
SIMPLE ENCODING/DECODING TECHNIQUE FOR CODE POSITION MODULATION
App. No. 10/029,038
→
INTEGRATED CIRCUIT HAVING AN FM DEMODULATOR AND METHOD THEREFOR
App. No. 10/115,124
→
METHOD FOR CLAMPING A SEMICONDUCTOR DEVICE IN A MANUFACTURING PROCESS
App. No. 10/112,271
→
METHOD FOR FORMING A SPUTTERED LAYER AND APPARATUS THEREFOR
App. No. 10/109,281
→
MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF FABRICATION THEREOF
App. No. 10/109,429
→
MULTIPLIER CELL AND METHOD OF COMPUTING
App. No. 10/105,543
→
LITHOGRAPHIC TEMPLATE AND METHOD OF FORMATION AND USE
App. No. 10/103,608
→
TRANSISTOR WITH LAYERED HIGH-K GATE DIELECTRIC AND METHOD THEREFOR
App. No. 10/098,706
→
SEMICONDUCTOR DEVICE HAVING A WIRE BOND PAD AND METHOD THEREFOR
App. No. 10/097,059
→
ADJUSTABLE GAIN CONTROL SYSTEM AND METHOD THEREOF
App. No. 10/092,968
→
INTEGRATED CIRCUIT STRUCTURE WITH DIELECTRIC ISLANDS IN METALLIZED REGIONS
App. No. 10/091,998
→
METHOD FOR MAKING A SEMICONDUCTOR DEVICE BY VARIABLE CHEMICAL MECHANICAL POLISH DOWNFORCE
App. No. 10/091,629
→
REFERENCE VOLTAGE GENERATOR FOR MRAM AND METHOD
App. No. 10/090,905
→
APPARATUS AND METHOD FOR DIGITAL CONTROL SYSTEMS
App. No. 10/084,988
→
METHOD FOR MANUFACTURING A LITHOGRAPHIC RETICLE FOR TRANSFERRING AN INTEGRATED CIRCUIT DESIGN TO A SEMICONDUCTOR WAFER
App. No. 10/085,960
→
METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT THEREOF
App. No. 10/086,079
→
INTEGRATED CIRCUIT TESTING WITH A VISUAL INDICATOR
App. No. 10/075,047
→
METHOD FOR PROCESSING SEMICONDUCTOR WAFERS IN AN ENCLOSURE WITH A TREATED INTERIOR SURFACE
App. No. 10/060,539
→
ELECTRICALLY SMALL PLANAR UWB ANTENNA APPARATUS AND RELATED SYSTEM
App. No. 10/054,790
→
MRAM WITHOUT ISOLATION DEVICES
App. No. 10/051,646
→
METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING INTERCONNECT BARRIER LAYERS
App. No. 10/051,262
→
STEP-DOWN CLOCK CONTROL AND METHOD FOR IMPROVING CONVERGENCE FOR A DIGITALLY CONTROLLED SELF-CALIBRATING VCO
App. No. 10/047,189
→
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING
App. No. 10/045,863
→