Patent Assignment
Reel/Frame 015930/0658
Merger
Recorded: 2005-03-21
Pages: 4
Assignor
AXIS SYSTEMS, INC.
Executed: 2004-04-01
Assignee
VERISITY DESIGN, INC., A CORP. OF CALIFORNIA
2041 LANDINGS DRIVE, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Property
(1)
Method and Apparatus for Simulating a Circuit Using Timing Insensitive Glitch-Free (Tigf) Logic
Patent:
8,244,512 →
Application:
09/954,989 →
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 12, 2002
From: TSENG, PING-SHENG; LIN, SHARON SHEAU-PYNG; SHEN, QUINCY KUN-HSU; TSAI, MIKE MON YEN
To: AXIS SYSTEMS, INC.
Reel/Frame 012609/0632 →
Assignment of Assignor's Interest
Jul 5, 2012
From: VERISITY DESIGN, INC.
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 028496/0022 →