Patent Assignment
Reel/Frame 028496/0022
Assignment of Assignor's Interest
Recorded: 2012-07-05
Pages: 4
Assignor
VERISITY DESIGN, INC.
Executed: 2012-06-29
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 94303
Covered Property
(1)
Method and Apparatus for Simulating a Circuit Using Timing Insensitive Glitch-Free (Tigf) Logic
Patent:
8,244,512 →
Application:
09/954,989 →
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 12, 2002
From: TSENG, PING-SHENG; LIN, SHARON SHEAU-PYNG; SHEN, QUINCY KUN-HSU; TSAI, MIKE MON YEN
To: AXIS SYSTEMS, INC.
Reel/Frame 012609/0632 →
Merger
Mar 21, 2005
From: AXIS SYSTEMS, INC.
To: VERISITY DESIGN, INC., A CORP. OF CALIFORNIA
Reel/Frame 015930/0658 →