Patent Assignment
Reel/Frame 018855/0591
Security Agreement
Recorded: 2007-02-06
Received: 2007-02-06
Pages: 11
Assignor
QSPEED SEMICONDUCTOR, INC.
Executed: 2007-01-23
Assignee
SILICON VALLEY BANK
3979 FREEDOM CIRCLE, SUITE 600, SANTA CLARA, CA, 95054, UNITED STATES
Covered Properties
(31)
Jfet and Mesfet Structures for Low Voltage High Current and High Frequency Applications
Application:
11/121,381 →
Pipelined Stop, Start, Address Byte, and Data Byte Technique and Circuit for I2C Logic System
Application:
11/032,272 →
Schottky Barrier Rectifier and Method of Manufacturing the Same
Application:
10/869,718 →
Method and Structure for Double Dose Gate in a Jfet
Application:
10/867,972 →
Vertical field effect transistor (FET) using deposited lateral gate
Application:
60/578,963 →
Junction effect field transistor (JFET) gated schottky diode as embedded body diode in power MOS device
Application:
60/579,020 →
Device structures of normally on and normally off JFETs with multiple doped gate and multiple conduction channel doping
Application:
60/563,596 →
Electrostatic Discharge Protection Device for Integrated Circuits
Application:
10/793,077 →
Method for a Junction Field Effect Transistor with Reduced Gate Capacitance
Application:
10/776,487 →
Flip-Chip Packaging
Application:
10/728,449 →
Starter Device for Normally Off Jfets
Application:
10/609,253 →
Method and Structure for Composite Trench Fill
Application:
10/439,558 →
Guard Ring Structure and Method for Fabricating Same
Application:
10/379,768 →
Dual Gate Structure for a Fet and Method for Fabricating Same
Application:
10/382,344 →
Buck-Boost Circuit with Normally Off Jfet
Application:
10/371,856 →
Two Terminal Rectifier Using Normally Off Jfet
Application:
10/360,450 →
Programmable Junction Field Effect Transistor and Method for Programming Same
Application:
10/335,403 →
Electrostatic Discharge Protection Device for Integrated Circuits
Application:
10/279,806 →
Structure for a Junction Field Effect Transitor with Reduced Gate Capacitance
Application:
10/278,303 →
Flip-Chip Packaging
Application:
10/215,570 →
Mosfet Driver Matching Circuit for an Enhancement Mode Jfet
Application:
10/209,211 →
Method and Structure for Double Dose Gate in a Jfet
Application:
10/191,030 →
Structure for Reduced Gate Capacitance in a Jfet
Application:
10/158,326 →
Jfet and Mesfet Structures for Low Voltage, High Current and High Frequency Applications
Application:
10/153,012 →
Method and Structure for a High Voltage Junction Field Effect Transistor
Application:
10/117,019 →
Pill and Capsule Counter
Application:
10/086,976 →
Full Wave Rectifier Circuit Using Normally Off Jfets
Application:
09/915,987 →
Semiconductor Package for Power Jfet Having Copper Plate for Source and Ribbon Contact for Gate
Application:
09/892,128 →
Boost Circuit with Normally Off Jfet
Application:
09/877,351 →
Power Supply Module in Integrated Circuits
Application:
09/835,616 →
Buck converter with normally off JFET
Application:
09/785,972 →