Patent Assignment
Reel/Frame 019047/0554
Assignment of Assignor's Interest
Recorded: 2007-03-22
Received: 2007-03-22
Pages: 6
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2007-01-31
Assignee
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Properties
(28)
A Void-Free Interlayer Dielectric (ILD0) for 0.18-Micron Flash Memory Semiconductor Device
Application:
10/244,129 →
Nitride Barrier Layer for Protection of Ono Structure from Top Oxide Loss in Fabrication of Sonos Flash Memory
Application:
10/158,044 →
Password and Dynamic Protection of Flash Memory Data
Application:
10/091,767 →
Switched-Capacitor Controller to Control the Rise Times of on-Chip Generated High Voltages
Application:
10/015,033 →
Nitride Barrier Layer for Protection of Ono Structure from Top Oxide Loss in a Fabrication of Sonos Flash Memory
Application:
09/966,702 →
Oxide/Nitride or Oxide/Nitride/Oxide Thickness Measurement Using Scatterometry
Application:
09/904,089 →
Multi Wire Insulation Displacement Contact and a Method of Making Multi Wire Terminations
Application:
09/881,541 →
Method and System for Qualifying an Ono Layer in a Semiconductor Device
Application:
09/875,073 →
Method and System for Qualifying an Ono Layer in a Semiconductor Device
Application:
09/875,056 →
Threshold Voltage Compacting for Non-Volatile Semiconductor Memory Designs
Application:
09/851,773 →
Method and System for Reducing Thinning of Field Isolation Structures in a Flash Memory Device
Application:
09/844,692 →
Accurate Verify Apparatus and Method for nor Flash Memory Cells in the Presence of High Column Leakage
Application:
09/842,288 →
System and Method for Erase Test of Integrated Circuit Device Having Non-Homogeneously Sized Sectors
Application:
09/836,065 →
Formation of Non-Volatile Memory Device Comprised of an Array of Vertical Field Effect Transistor Structures
Application:
09/817,628 →
High Voltage Oxidation Method for Highly Reliable Flash Memory Devices
Application:
09/803,400 →
Configure Registers and Loads to Tailor a Multi-Level Cell Flash Design
Application:
09/794,479 →
Address Broadcasting to a Paged Memory Device to Eliminate Access Latency Penalty
Application:
09/794,478 →
Ascending Staircase Read Technique for a Multilevel Cell Nand Flash Memory Device
Application:
09/794,480 →
Staircase Program Verify for Multi-Level Cell Flash Memory Designs
Application:
09/794,482 →
Descending staircase read technique for a multilevel cell NAND flash memory device
Application:
09/794,485 →
Method of Forming a Void-Free Interlayer Dielectric (ILD0) for 0.18-Um Flash Memory Technology and Semiconductor Device Thereby Formed
Application:
09/788,045 →
Piggyback Programming Using an Extended First Pulse for Multi-Level Cell Flash Memory Designs
Application:
09/779,794 →
Concurrent Program Reconnaissance with Piggyback Pulses for Multi-Level Cell Flash Memory Designs
Application:
09/779,764 →
Piggyback Programming Using Voltage Control for Multi-Level Cell Flash Memory Designs
Application:
09/779,821 →
Program Reconnaissance to Eliminate Variations in Vt Distributions of Multi-Level Cell Flash Memory Designs
Application:
09/779,864 →
Piggyback Programming Using Graduated Steps for Multi-Level Cell Flash Memory Designs
Application:
09/779,225 →
Piggyback Programming Using Timing Control for Multi-Level Cell Flash Memory Designs
Application:
09/779,792 →
Piggyback Programming with Staircase Verify for Multi-Level Cell Flash Memory Designs
Application:
09/779,884 →