Patent Assignment
Reel/Frame 019263/0134
Assignment of Assignor's Interest
Recorded: 2007-05-08
Pages: 6
Assignor
MAYDER, ROMI O.
Executed: 2007-03-10
Assignee
SILICON TEST SYSTEMS, INC.
1331 SIERRA AVENUE, SAN JOSE, CALIFORNIA, 95126
Covered Property
(1)
Low Cost, High Pin Count, Wafer Sort Automated Test Equipment (Ate) Device Under Test (Dut) Interface for Testing Electronic Devices in High Parallelism
Application:
11/685,857 →
Publication:
US 2008/0100323
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 9, 2009
From: SILICON TEST SYSTEMS, INC.
To: VERIGY (SINGAPORE) PTE. LTD.
Reel/Frame 022078/0762 →
Corrective Assignment to Correct the Serial No.: 11/685,587 Should Actually Be 11/685,857. Previously Recorded on Reel 022078 Frame 0762. Assignor(S) Hereby Confirms the Assignment.
Jan 15, 2009
From: SILICON TEST SYSTEMS, INC.
To: VERIGY (SINGAPORE) PTE. LTD.
Reel/Frame 022118/0140 →