Patent Assignment

Assignment of Assignor's Interest

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Low Cost, High Pin Count, Wafer Sort Automated Test Equipment (Ate) Device Under Test (Dut) Interface for Testing Electronic Devices in High Parallelism

Solid High Aspect Ratio via Hole Used for Burn-in Boards, Wafer Sort Probe Cards, and Package Test Load Boards with Electronic Circuitry

High Voltage, High Frequency, High Reliability, High Density, High Temperature Automated Test Equipment (Ate) Switch Design

High Impedance, High Parallelism, High Temperature Memory Test System Architecture

Three-Dimensional Printed Circuit Board for Use with Electronic Circuitry

A Method of Fabricating a Probe Card Assembly Using Magnetically Aligned Electrical Contact Elements, a Stamped Construction Electrical Contact Element Usable with the Method, and a Standalone Probe Card Tester Formable Using the Method

Low Cost, High Pin Count, Wafer Sort Ate Dut Interface Used for Testing Electronic Devices in High Parallelism

Three Dimensional Printed Circuit Board with Electronic Circuitry

Solid High Aspect Ratio via Hole Used for Burn-in Boards, Wafer Sort Probe Cards, and Package Test Load Boards with Electronic Circuitry

High Impedance, High Parallelism, High Temperature Memory Test System Architecture

Method and Apparatus for Manufacturing a High Parallelism, Low Cost Probe Card Using Magnetic Electrical Contacts with Optional Electronic Circuitry for Production Testing of Memory Devices