Patent Assignment
Reel/Frame 022118/0140
Corrective Assignment to Correct the Serial No.: 11/685,587 Should Actually Be 11/685,857. Previously Recorded on Reel 022078 Frame 0762. Assignor(S) Hereby Confirms the Assignment.
Recorded: 2009-01-15
Pages: 6
Assignor
SILICON TEST SYSTEMS, INC.
Executed: 2008-12-26
Assignee
VERIGY (SINGAPORE) PTE. LTD.
NO. 1 YISHUN AVENUE 7, LOT 1937C, 1935X, 1975P, SINGAPORE, 768923, SINGAPORE
Covered Property
(1)
Low Cost, High Pin Count, Wafer Sort Automated Test Equipment (Ate) Device Under Test (Dut) Interface for Testing Electronic Devices in High Parallelism
Application:
11/685,857 →
Publication:
US 2008/0100323
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.