Assignment of Assignor's Interest

Recorded: 2007-05-10 Pages: 2

Assignor

INOUE, MASATO

Executed: 2007-02-16

Assignee

FUJITSU LIMITED

1-1, KAMIKODANAKA 4-CHOME NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN

Covered Property (1)

Method of Designing and Manufacturing Semiconductor Integrated Circuit Device Using Master Slice Method

Application: 11/798,165 →

Publication: US 2007/0284712

Related Assignments (2)

Other recorded transfers of the patent in this record — the chain of ownership.