Semiconductor integrated circuit device, and method of designing and manufacturing the same
Disclosed are a semiconductor integrated circuit device, and a design and manufacturing method of the device, in which various semiconductor integrated circuit devices can be effectively designed and manufactured at low cost using a master slice method. A fixed layer used in common between Wire-Bonding (WB) chips and Flip-Chip (FC) chips is previously designed. When it is determined whether to form a WB chip or a FC chip, a variable layer for the WB chip or for the FC chip is designed. Based on this design, the WB chip or FC chip including the fixed layer and the variable layer added thereto is formed. Since the WB chip and the FC chip are differentially formed by the variable layer, the designing and manufacturing man-hour can be concentrated on the variable layer. Thus, reduction in TAT and in cost can be realized in design and manufacture of the device.
1 . A method of designing a semiconductor integrated circuit device, comprising the steps of:
designing a first layer which constitutes a portion including no pads of the semiconductor integrated circuit device, the first layer being used in common regardless of a package type of the semiconductor integrated circuit device; and
designing depending on the package type a second layer which constitutes a portion over the first layer of the semiconductor integrated circuit device.
2 . The method according to claim 1 , wherein, in a case of forming the pad on the semiconductor integrated circuit device, the pad is formed in the second layer.
3 . The method according to claim 1 , wherein an input/output buffer formed on the semiconductor integrated circuit device is formed only in the first layer.
4 . The method according to claim 1 , wherein an input/output buffer formed on the semiconductor integrated circuit device is formed in the first and second layers.
5 . The method according to claim 1 , wherein, in a case of forming on the semiconductor integrated circuit device the pad and a power reinforcing wire for connecting between the pad and a core of the semiconductor integrated circuit device, the pad and the wire are formed in the second layer.
6 . The method according to claim 1 , wherein, in a case of forming the pad on the semiconductor integrated circuit device, the pad and a wire for connecting between the pad and an input/output buffer formed on the semiconductor integrated circuit device are formed in the second layer.
7 . The method according to claim 1 , wherein, in a case of forming a bump on the semiconductor integrated circuit device, the bump and a wire connected with the bump are formed in the second layer.
8 . A semiconductor integrated circuit device, comprising:
a first layer which constitutes a portion including no pads of the semiconductor integrated circuit device, the first layer being used in common regardless of a package type of the semiconductor integrated circuit device; and
a second layer which constitutes a portion over the first layer of the semiconductor integrated circuit device, the second layer being formed depending on the package type.
9 . The device according to claim 8 , wherein the pad is formed in the second layer.
10 . The device according to claim 8 , further comprising an input/output buffer, wherein the input/output buffer is formed only in the first layer.
11 . The device according to claim 8 , further comprising an input/output buffer, wherein the input/output buffer is formed in the first and second layers.
12 . The device according to claim 8 , further comprising the pad and a power reinforcing wire for connecting between the pad and a core and wherein the pad and the wire are formed in the second layer.
13 . The device according to claim 8 , further comprising the pad, an input/output buffer, and a wire for connecting between the pad and the input/output buffer, wherein the pad and the wire are formed in the second layer.
14 . The device according to claim 8 , further comprising a bump, an input/output buffer, and a wire connected with the bump, wherein the bump and the wire are formed in the second layer.
15 . A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
forming a first layer which constitutes a portion including no pads of the semiconductor integrated circuit device, the first layer being used in common regardless of a package type of the semiconductor integrated circuit device; and
forming depending on the package type a second layer which constitutes a portion over the first layer of the semiconductor integrated circuit device.
16 . The method according to claim 15 , wherein, in the second layer forming step, the second layer is formed such that the pad is formed in the second layer.
17 . The method according to claim 15 , wherein, in the first and second layer forming steps, the first and second layers are formed such that an input/output buffer of the semiconductor integrated circuit device is formed only in the first layer or formed in the first and second layers.
18 . The method according to claim 15 , wherein, in the second layer forming step, the second layer is formed such that the pad and a power reinforcing wire for connecting between the pad and a core of the semiconductor integrated circuit device are formed in the second layer.
19 . The method according to claim 15 , wherein, in the second layer forming step, the second layer is formed such that the pad and a wire for connecting between the pad and an input/output buffer of the semiconductor integrated circuit device are formed in the second layer.
20 . The method according to claim 15 , wherein, in the second layer forming step, the second layer is formed such that a bump of the semiconductor integrated circuit device and a wire connected with the bump are formed in the second layer.