Patent Assignment
Reel/Frame 021138/0345
FIRST AMENDMENT TO MANNINGTON MILLS, INC. SECOND AMENDED AND RESTATED PATENT SECURITY AGREEMENT
Recorded: 2008-06-24
Received: 2008-06-24
Pages: 9
Assignor
MANNINGTON MILLS, INC.
Executed: 2008-06-20
Assignee
BANK OF AMERICA, N.A.
335 MADISON AVENUE, NEW YORK, NY, 10017, UNITED STATES
Covered Applications
(79)
CONFIGURABLE DEMODULATOR AND DEMODULATION METHOD
App. No. 12/028,292
→
DIGITAL DATA ENCODING AND DECODING METHOD AND SYSTEM
App. No. 12/027,703
→
MULTI-FORMAT ALL-DIGITAL MODULATOR AND METHOD
App. No. 12/027,692
→
THICK METAL INTERCONNECT WITH METAL PAD CAPS AT SELECTIVE SITES AND PROCESS FOR MAKING THE SAME
App. No. 12/012,121
→
THICK METAL INTERCONNECT WITH METAL PAD CAPS AT SELECTIVE SITES AND PROCESS FOR MAKING THE SAME
App. No. 12/012,120
→
SURFACE COVERINGS CONTAINING ALUMINUM OXIDE
App. No. 11/976,577
→
HIGH TEMPERATURE RANGE ELECTRICAL CIRCUIT TESTING
App. No. 11/871,716
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PADE' APPROXIMANT BASED COMPENSATION FOR INTEGRATED SENSOR MODULES AND THE LIKE
App. No. 11/700,475
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CURRENT PROTECTION CIRCUIT USING MULTIPLE SEQUENCED BIPOLAR TRANSISTORS
App. No. 11/567,688
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MULTI-PAD SHARED CURRENT DISSIPATION WITH HETEROGENIC CURRENT PROTECTION STRUCTURES
App. No. 11/532,478
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SINGLE WELL EXCESS CURRENT DISSIPATION CIRCUIT
App. No. 11/532,477
→
NON-LINEAR SENSOR TEMPERATURE COMPENSATION USING SUMMED TEMPERATURE COMPENSATION SIGNALS
App. No. 11/460,948
→
SENSOR CALIBRATION USING SELECTIVELY DISCONNECTED TEMPERATURE
App. No. 11/460,951
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INITIAL DECISION-POINT CIRCUIT OPERATION MODE
App. No. 11/371,661
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Flooring products and methods of making the same
App. No. 11/192,552
→
CONNECTING SYSTEM FOR SURFACE COVERINGS
App. No. 11/190,452
→
DIFFERENTIAL SIGNAL DRIVER HAVING COMPLIMENTARY AND CURRENT-AIDED PRE-EMPHASIS
App. No. 11/157,403
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VARIABLE TWIST LEVEL YARN USING FLUID TWISTING
App. No. 11/155,196
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LOW POWER SIGMA DELTA MODULATOR
App. No. 11/132,705
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PROVIDING NONLINEAR TEMPERATURE COMPENSATION FOR SENSING MEANS BY USE OF PADE APPROXIMANT FUNCTION EMULATORS
App. No. 11/123,964
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CLOSED LOOP DIRECT CURRENT TO DIRECT CURRENT CONVERTER THAT DOES NOT REQUIRE VOLTAGE REFERENCE
App. No. 11/119,452
→
HIGH RELIABILITY ELECTRICALLY ERASABLE AND PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
App. No. 11/098,940
→
TRACK AND HOLD CIRCUIT WITH OPERATING POINT SENSITIVE CURRENT MODE BASED OFFSET COMPENSATION
App. No. 11/094,945
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METHOD AND SYSTEM FOR DATA LOGGING IN A LISTENING DEVICE
App. No. 11/091,747
→
METHOD AND SYSTEM FOR PROTECTING CONTENT IN A PROGRAMMABLE SYSTEM
App. No. 11/091,746
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SURFACE COVERINGS CONTAINING FUSED RECYCLED MATERIAL AND PROCESSES OF MAKING THE SAME
App. No. 11/027,042
→
DOUBLE-SIDED EXTENDED DRAIN FIELD EFFECT TRANSISTOR
App. No. 11/010,892
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RADIO FREQUENCY ENVELOPE DETECTOR
App. No. 10/977,295
→
DYNAMIC PHASE ALIGNMENT OF A CLOCK AND DATA SIGNAL USING AN ADJUSTABLE CLOCK DELAY LINE
App. No. 10/933,742
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TEXTILE SUBSTRATE HAVING LOW VARIABLE TWIST YARN
App. No. 10/925,607
→
AMBIENT LIGHT SUPPRESSION CIRCUIT FOR PHOTODIODE RECEIVER APPLICATIONS
App. No. 10/925,263
→
HIGH VOLTAGE, LOW-OFFSET OPERATIONAL AMPLIFIER WITH RAIL-TO-RAIL COMMON MODE INPUT RANGE IN A DIGITAL CMOS PROCESS
App. No. 10/919,757
→
LOW-VOLTAGE DIFFERENTIAL SIGNAL (LVDS) TRANSMITTER WITH HIGH SIGNAL INTEGRITY
App. No. 10/920,009
→
THERMOPLASTIC PLANKS AND METHODS FOR MAKING THE SAME
App. No. 10/909,684
→
OPTICAL TRACKING SENSOR METHOD
App. No. 10/903,790
→
DIE IDENTIFICATION SYSTEMS AND METHODS
App. No. 10/883,316
→
METHODS FOR MANUFACTURING A SOFT ERROR AND DEFECT RESISTANT PRE-METAL DIELECTRIC LAYER
App. No. 10/877,482
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REACTIVE SENSOR MODULES USING PADE' APPROXIMANT BASED COMPENSATION AND PROVIDING MODULE-SOURCED EXCITATION
App. No. 10/870,314
→
STRUCTURED ASIC DEVICE WITH CONFIGURABLE DIE SIZE AND SELECTABLE EMBEDDED FUNCTIONS
App. No. 10/860,894
→
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
App. No. 10/857,409
→
PADE' APPROXIMANT BASED COMPENSATION FOR INTEGRATED SENSOR MODULES AND THE LIKE
App. No. 10/845,681
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CARPET USING USING UNUSED YARN
App. No. 10/782,631
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TEMPERATURE STABLE VOLTAGE REFERENCE CIRCUIT USING A METAL-SILICON SCHOTTKY DIODE FOR LOW VOLTAGE CIRCUIT APPLICATIONS
App. No. 10/770,233
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METHOD AND SYSTEM FOR PROCESSING SUBBAND SIGNALS USING ADAPTIVE FILTERS
App. No. 10/642,847
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DIGITALLY CONTROLLED IMPEDANCE DRIVER MATCHING FOR WIDE VOLTAGE SWINGS AT INPUT/OUTPUT NODE AND HAVING PROGRAMMABLE STEP SIZE
App. No. 10/637,840
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DUAL DIFFERENTIAL-INPUT AMPLIFIER HAVING WIDE INPUT RANGE
App. No. 10/615,440
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DOUBLE-SIDED EXTENDED DRAIN FIELD EFFECT TRANSISTOR, AND INTEGRATED OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION CIRCUIT THAT USES THE SAME
App. No. 10/611,714
→
DELAY LOCKED LOOP WITH FIXED ANGLE DE-SKEW, QUICK START AND LOW JITTER
App. No. 10/602,195
→
SYMMETRIC AND COMPLEMENTARY DIFFERENTIAL AMPLIFIER
App. No. 10/446,306
→
BI-DIRECTIONAL CURRENT MEASUREMENT CIRCUIT THAT USES A TRANSCONDUCTANCE AMPLIFIER TO GENERATE A COPY CURRENT
App. No. 10/442,618
→
MULTI-FAULT PROTECTED HIGH SIDE SWITCH WITH CURRENT SENSE
App. No. 10/442,630
→
DIRECT CONVERSION RECEIVER WITH DIRECT CURRENT OFFSET CORRECTION CIRCUITRY
App. No. 10/430,656
→
ADAPTIVE DIVERSITY RECEIVER ARCHITECTURE
App. No. 10/430,455
→
DIRECT CONVERSION RECEIVER FOR AMPLITUDE MODULATED SIGNALS USING LINEAR/LOG FILTERING
App. No. 10/426,383
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UP-CONVERSION OF A DOWN-CONVERTED BASEBAND SIGNAL IN A DIRECT CONVERSION ARCHITECTURE WITHOUT THE BASEBAND SIGNAL PASSING THROUGH ACTIVE ELEMENTS
App. No. 10/426,225
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DISTRIBUTED MEMORY AND LOGIC CIRCUITS
App. No. 10/422,137
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STATIC RANDOM ACCESS MEMORY (SRAM) WITHOUT PRECHARGE CIRCUITRY
App. No. 10/406,526
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SWITCHED CAPACITOR VOLTAGE REFERENCE CIRCUITS USING TRANSCONDUCTANCE CIRCUIT TO GENERATE REFERENCE VOLTAGE
App. No. 10/401,082
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STABLE FLOATING GATE VOLTAGE REFERENCE USING INTERCONNECTED CURRENT-TO-VOLTAGE AND VOLTAGE-TO-CURRENT CONVERTERS
App. No. 10/393,333
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DIFFERENTIAL NOR MEMORY CELL HAVING TWO FLOATING GATE TRANSISTORS
App. No. 10/387,824
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STIMULATED QUICK START OSCILLATOR
App. No. 10/384,094
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LOW VOLTAGE ENHANCED OUTPUT IMPEDANCE CURRENT MIRROR
App. No. 10/373,912
→
METHODS FOR SIDEWALL PROTECTION OF METAL INTERCONNECT FOR UNLANDED VIAS USING PHYSICAL VAPOR DEPOSITION
App. No. 10/373,911
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USE OF IRREGULARLY SHAPED CONDUCTIVE FILLER FEATURES TO IMPROVE PLANARIZATION OF THE CONDUCTIVE LAYER WHILE REDUCING PARASITIC CAPACITANCE INTRODUCED BY THE FILLER FEATURES
App. No. 10/348,093
→
METHOD AND SYSTEM FOR REAL-TIME SPEECH RECOGNITION
App. No. 10/277,454
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METHOD AND SYSTEM FOR REAL TIME AUDIO SYNTHESIS
App. No. 10/277,598
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ABSOLUTE VALUE AMPLITUDE BASEBAND DETECTOR
App. No. 10/262,437
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INTEGRATED OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION CIRCUIT
App. No. 10/243,749
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METHOD FOR ASSEMBLING A REPEATING SERIES OF TILES
App. No. 10/140,300
→
BANDGAP VOLTAGE REFERENCE USING DIFFERENTIAL PAIRS TO PERFORM TEMPERATURE CURVATURE COMPENSATION
App. No. 10/134,108
→
THERMOPLASTIC PLANKS AND METHODS FOR MAKING THE SAME
App. No. 10/104,383
→
REFERENCE-FREE CHARGE TRANSFER AMPLIFIER
App. No. 10/034,801
→
LISTENING DEVICE
App. No. 10/023,109
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DUAL DIE MEMORY
App. No. 10/014,928
→
CIRCUITS AND METHODS FOR INITIALIZING MEMORY CELLS
App. No. 10/016,163
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SURFACE COVERINGS CONTAINING ALUMINUM OXIDE
App. No. 09/930,705
→
Circuits and methods for providing a current reference with a controlled temperature coefficient using a series composite resistor
App. No. 09/834,421
→
Circuits and methods for providing a bandgap voltage reference using composite resistors
App. No. 09/834,709
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SRAM ROW REDUNDANCY
App. No. 09/799,884
→