Distributed memory and logic circuits
View Patent ↗Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.
1. An integrated circuit comprising:
a plurality of columns of memory;
a plurality of columns of logic circuits, wherein each of the columns of memory is disposed adjacent to one of the columns of logic circuits, with the plurality of columns of memory forming at least one block of memory having rows which extend through the plurality of columns of memory and comprises a fully interconnected memory, with each of the columns of memory partitioned into groups of memory cells; and
a decode circuit, coupled to the plurality of columns of memory, adapted to control word lines extending through the plurality of columns of memory, wherein the decode circuit is disposed in a column centrally located among the plurality of columns of memory.
2. The integrated circuit of claim 1 , wherein each of the groups of memory cells is configured as a two by four memory block, with each memory cell being a two port static random access memory.
3. The integrated circuit of claim 1 , further comprising read/write circuits, coupled to corresponding ones of the plurality of columns of memory, adapted to provide read/write capability via associated bit lines to the memory cells within the plurality of columns of memory.
4. The integrated circuit of claim 3 , wherein the read/write circuits are disposed in a row centrally located within an area occupied by the plurality of columns of memory.
5. The integrated circuit of claim 3 , wherein the read/write circuits perform a differential write via the associated bit lines and a single-ended read via one of the associated bit lines.
6. The integrated circuit of claim 3 , wherein the read/write circuits further comprise:
a first transistor, coupled to a first one of the associated bit lines; and
a second transistor, coupled to a second one of the associated bit lines, wherein the second one of the associated bit lines controls a gate voltage of the first transistor and the first one of the associated bit lines controls a gate voltage of the second transistor to equalize a rise/fall time of signal levels on the associated bit lines.
7. The integrated circuit of claim 1 , further comprising a clock row adapted to provide clock signals to the plurality of columns of memory and the plurality of columns of logic circuits.
8. The integrated circuit of claim 7 , further comprising a power supply plane disposed around the plurality of columns of memory and the plurality of columns of logic circuits.
9. The integrated circuit of claim 1 , wherein interconnect lines are disposed above and/or below the plurality of columns of memory to provide routing capability to the plurality of columns of logic circuits.
10. The integrated circuit of claim 1 , wherein the plurality of columns of memory and the plurality of columns of logic circuits are replicated within the integrated circuit to form a plurality of the blocks of memory.
11. A circuit comprising:
a plurality of columns of memory;
a plurality of columns of circuits adaptable to perform logic functions, wherein each of the columns of memory is disposed adjacent to one of the plurality of columns of circuits, with the plurality of columns of memory forming at least one block of memory having rows which extend through the plurality of columns of memory; and
means for addressing and accessing memory cells within the at least one block of memory, wherein the means for addressing and accessing the memory cells is disposed in at least one row and column centrally located among the plurality of columns of memory.
12. The circuit of claim 11 , wherein each of the columns of memory is partitioned into groups of memory cells, with each memory cell being a two port static random access memory.
13. The circuit of claim 11 , wherein the means for addressing and accessing memory cells comprises:
decode circuitry adapted to control signal levels on word lines extending through the plurality of columns of memory; and
read/write circuitry adapted to provide read and write capability via bit lines to the plurality of columns of memory cells.
14. The circuit of claim 13 , wherein the read/write circuitry performs a differential write via the bit lines and a single-ended read via one of the bit lines, with a pair of transistors coupled to the bit lines and controlled by respective ones of the bit lines to equalize a rise/fall time of signal levels on the bit lines.
15. The circuit of claim 13 , wherein the circuit is replicated to form a plurality of the blocks of memory on an integrated circuit, and further comprising interconnect lines disposed above and/or below the plurality of columns of memory to provide interconnect routing to the plurality of columns of circuits.
16. A method of increasing utilization of logic circuits on an integrated circuit, the method comprising:
arranging the logic circuits in a plurality of columns;
disposing between each of the plurality of columns of the logic circuits a column of memory to reduce local interconnect congestion;
interconnecting each of the columns of memory to form at least one block of memory whose rows extend through the columns of memory; and
disposing read/write circuitry in a row centrally located within the at least one block of memory.
17. The method of claim 16 , further comprising providing interconnect structure above and/or below the columns of memory to provide additional routing capability to the logic circuits in the plurality of columns.
18. The method of claim 17 , further comprising partitioning each of the columns of memory into groups of memory cells, with each of the memory cells being two port static random access memory.
19. The method of claim 16 , further comprising disposing decode circuitry in a column centrally located within the at least one block of memory.