Thick metal interconnect with metal pad caps at selective sites and process for making the same
View Patent ↗The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.
1. A substrate ( 100 ) having thick metal interconnects of high conductivity power metal ( 115 ) with metal caps ( 117 / 118 ), comprising:
(a) at least one integrated circuit fabricated on said substrate ( 100 ), said at least one integrated circuit having at least one metallization layer ( 107 );
(b) an insulating layer ( 112 ) overlaying said at least one metallization layer ( 107 ), and wherein at least a portion of said at least one metallization layer ( 107 ) is exposed;
(c) at least one high conductivity power metal interconnection ( 115 ) making electrical contact with said at least one metallization layer ( 107 );
(d) at least one flowable dielectric layer ( 116 ) overlaying said high conductivity power metal interconnection ( 115 ) and having at least one opening ( 135 ) to expose a portion of the surface of said high conductivity power metal interconnection ( 115 ); and
(e) a metal cap ( 117 / 118 ) disposed over said at least one opening ( 135 ) and making electrical contact with said high conductivity power metal interconnection ( 115 ).
2. The substrate of claim 1 , wherein said integrated circuit includes at least one power transistor.
3. The substrate of claim 1 , wherein said insulating film is selected from a group consisting of Silicon Nitride, Silicon Oxy-Nitride, Silicon Oxide, Organo-Silicate Glass (SOG), Polyimides, and combinations thereof.
4. The substrate of claim 1 , wherein at least a portion of the wall of said opening in said insulating layer is tapered.
5. The substrate of claim 1 , wherein the wall of said opening in said insulating layer overlaps at least a portion of said metallization layer, and wherein said overlap is at least about 2 um.
6. The substrate of claim 1 , wherein said high conductivity power metal interconnect comprises of at least one barrier layer and at least one high conductivity metal layer.
7. The substrate of claim 6 , wherein said at least one barrier layer is selected from a group consisting of Ti, TiN, TiW, Cr, Ta, TaN, and combinations thereof.
8. The substrate of claim 6 , wherein said at least one high conductivity metal layer is selected from a group consisting of Copper and Gold.
9. The substrate of claim 6 , wherein the thickness of said at least one barrier layer is at least about 2 kA.
10. The substrate of claim 6 , wherein the thickness of said at least one high conductivity metal layer is between about 5 um to about 50 um, and preferably between about 5 um to about 30 um.
11. The substrate of claim 1 , wherein said flowable dielectric layer is selected from a group consisting of Polyimide, BCB, Ortho Silicate Glass, and combinations thereof.
12. The substrate of claim 1 , wherein the surface of said flowable dielectric layer and said high conductivity power metal interconnect is selected from a group consisting of planar surface and non-planar surface.
13. The substrate of claim 1 , wherein said metal cap comprises of at least one barrier layer and at least one wire bondable metal layer.
14. The substrate of claim 13 , wherein said at least one barrier layer is selected from a group consisting of Ti, TiN, TiW, Cr, Ta, TaN, and combinations thereof.
15. The substrate of claim 13 , wherein said at least one wire bondable metal layer is selected from a group consisting of Nickel, Nickel-Phosphorus, Aluminum, Aluminum-Silicon, Aluminum-Copper, Aluminum-Copper-Silicon, Gold, and combinations thereof.
16. The substrate of claim 13 , wherein the thickness of said at least one barrier layer is at least about 2 kA.
17. The substrate of claim 13 , wherein the thickness of said at least one wire bondable metal layer is at least about 1 um.
18. The substrate of claim 1 , wherein said wire bondable metal cap layer is larger than said opening in said dielectric layer.
19. A substrate ( 100 ) having interconnections of high conductivity power metal ( 115 ) with metal caps ( 125 / 127 ), comprising:
(a) an integrated circuit of semiconductor devices fabricated on said substrate ( 100 ), said circuit having at least one metallization layer ( 107 );
(b) an insulating layer ( 112 ) overlaying said metallization layer ( 107 ) and said substrate ( 100 ), having holes ( 154 ) and lines ( 154 ) exposing at least a portion of said metallization layer ( 107 );
(c) a high conductivity interconnect power metal interconnection ( 115 ) disposed over said holes ( 154 ) and lines ( 154 ) and making electrical contact with said metallization layer ( 107 );
(d) a flowable dielectric layer ( 116 ) overlaying said high conductivity interconnect power metal interconnection ( 115 ) and said substrate ( 100 ), and having an opening ( 125 / 127 ) at selected region ( 125 / 127 ) to expose a portion of said high conductivity interconnect power metal interconnection surface ( 115 ); and
(e) a Nickel-Phosphorus/Gold cap ( 125 / 127 ) within said opening ( 135 ) at said selected region ( 135 ).
20. A substrate ( 100 ) having interconnections of high conductivity power metal ( 115 ), comprising:
(a) an integrated circuit of semiconductor devices fabricated on said substrate ( 100 ), said circuit having at least one metallization layer ( 107 );
(b) an insulating layer ( 112 ) overlaying said metallization layer ( 107 ) and said substrate ( 100 ), having holes ( 154 ) and lines ( 154 ) exposing a portion of said metallization layer ( 107 );
(c) a high conductivity power metal interconnect ( 115 ) disposed over said holes ( 154 ) and lines ( 154 ) and making electrical contact with said metallization layer ( 107 ); and
(d) at least one protective metallic coating ( 120 / 121 ) encasing at least a portion of said high conductivity power metal interconnect ( 115 ).
21. The substrate of claim 20 , wherein said semiconductor devices include at least one power transistor.
22. The substrate of claim 20 , wherein said insulating layer is selected from a group consisting of Silicon Nitride, Silicon Oxy-Nitride, Silicon Oxide, Organo-Silicate Glass (SOG), Polyimides, and combinations thereof.
23. The substrate of claim 20 , wherein at least a portion of the walls for said holes and lines in said insulating layer are tapered.
24. The substrate of claim 20 , wherein said high conductivity power interconnect metal is selected from a group consisting of a Titanium metal layer, and a Titanium-Nitride barrier metal layer with a copper metal layer.
25. The substrate of claim 20 , wherein said high conductivity power metal interconnect comprises of at least one barrier layer and at least one high conductivity metal layer.
26. The substrate of claim 20 , wherein said at least one barrier layer is selected from a group consisting of Ti, TiN, TiW, Cr, Ta, TaN, and combinations thereof.
27. The substrate of claim 20 , wherein said at least one high conductivity metal layer is Copper.
28. The substrate of claim 20 , wherein the thickness of said copper layer is between about 5 um to about 50 um, and preferably between about 5 um to about 35 um.
29. The substrate of claim 20 , wherein said metallic coating is selected from a group consisting of Nickel-Phosphorus and Gold.
30. The substrate of claim 20 , wherein said Nickel-Phosphorus layer contains between about 7 percent to about 11 percent Phosphorus.
31. The substrate of claim 20 , wherein the thickness of said Nickel-Phosphorus coating is at least about 1 um.
32. The substrate of claim 20 , wherein the thickness of said Gold layer is less than about 1.2 kA, and preferably less than about 1 kA.
33. A substrate ( 100 ) having interconnections of high conductivity power metal ( 115 ), comprising:
(a) an integrated circuit of semiconductor devices fabricated on said substrate ( 100 ), said circuit having at least one metallization layer ( 107 );
(b) an insulating layer ( 112 ) overlaying said metallization layer ( 107 ) and said substrate ( 100 ), and having holes ( 154 ) and lines ( 154 ) exposing a portion of said metallization layer ( 107 ); and
(c) a high conductivity interconnect metal ( 115 ) disposed over said holes ( 154 ) and lines ( 154 ) and making electrical contact with said metallization layer ( 107 ).
34. The substrate of claim 33 , wherein said semiconductor devices include power transistors.
35. The substrate of claim 33 , wherein said insulating film is selected from a group consisting of Silicon Nitride, Silicon Oxy-Nitride, Silicon Oxide, Organo-Silicate Glass (SOG), Polyimides, and combinations thereof.
36. The substrate of claim 33 , wherein at least a portion of the walls for said holes and lines in said insulating layer are tapered.
37. The substrate of claim 33 , wherein said high conductivity power metal comprises a TiW barrier layer and a gold metal layer.
38. The substrate of claim 37 , wherein the thickness of said TiW barrier layer is at least about 2 kA.
39. The substrate of claim 37 , wherein the thickness of said gold metal layer is between about 5 um to about 50 um, and preferably between about 5 um to about 35 um.
40. A substrate ( 100 ) having interconnections of high conductivity power metal ( 115 ), comprising:
(a) an integrated circuit of semiconductor devices fabricated on said substrate ( 100 ), said circuit having at least one metallization layer ( 107 );
(b) an insulating layer ( 112 ) overlaying said metallization layer ( 107 ) and said substrate ( 100 ), and having holes ( 154 ) and lines ( 154 ) exposing at least a portion of said metallization layer ( 107 ); and
(c) wherein at least a portion of said insulating layer ( 112 ) above said metallization layer ( 107 ) has a positive slope ( 136 ).