Patent Assignment
Reel/Frame 035190/0219
Assignment of Assignor's Interest
Recorded: 2015-03-18
Pages: 8
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2015-03-13
Assignee
ROUND ROCK RESEARCH, LLC
2001 ROUTE 46, WATERVIEW PLAZA, SUITE 310, PARSIPPANY, NEW JERSEY, 07054
Covered Properties
(36)
High Aspect Ratio Metallization Structures and Processes for Fabricating the Same
Patent:
6,121,134 →
Application:
09/063,608 →
Dual Damascene Interconnect
Patent:
6,534,866 →
Application:
09/548,472 →
High Aspect Ratio Metallization Structures
Patent:
6,495,921 →
Application:
09/584,004 →
Method and Apparatus for Providing a Secure-Private Partition on a Hard Disk Drive of a Computer System via Ide Controller
Patent:
7,155,615 →
Application:
09/608,117 →
System and Method for Protected Messaging
Peripheral Device with Hardware Linked List
Low Voltage Operation of Static Random Access Memory
Method of Forming a Dual Damascene Interconnect by Selective Metal Deposition
High Aspect Ratio Metallization Structures
Dual Damascene Interconnect
System and Method for Using a Learning Sequence to Establish Communications on a High-Speed Nonsynchronous Interface in the Absence of Clock Forwarding
Through-Wafer Interconnects for Photoimager and Memory Wafers
Methods of Forming Blind Wafer Interconnects
System and Method for Using a Learning Sequence to Establish Communications on a High- Speed Nonsynchronous Interface in the Absence of Clock Forwarding
Peripheral Device with Hardware Linked List
Methods of Forming Blind Wafer Interconnects, and Related Structures and Assemblies
Through-Wafer Interconnects for Photoimager and Memory Wafers
Method, Apparatus, and System for Erasing Memory
Programming a Memory Device to Increase Data Reliability
Dynamic Slc/Mlc Blocks Allocations for Non-Volatile Memory
Non-Volatile Memory with Extended Operating Temperature Range
Through-Wafer Interconnects for Photoimager and Memory Wafers
Method, Apparatus, and System for Erasing Memory
Voltage Discharge Circuits and Methods
Selective Error Control Coding in Memory Devices
Programming a Memory Device to Increase Data Reliability
Through-Wafer Interconnects for Photoimager and Memory Wafers
Semiconductor Dice Including at Least One Blind Hole, Wafers Including Such Semiconductor Dice, and Intermediate Products Made While Forming at Least One Blind Hole in a Substrate
Programming a Memory Device to Increase Data Reliability
Method for Discharging a Voltage from a Capacitance in a Memory Device
Semiconductor Dice Including at Least One Blind Hole, Wafers Including Such Semiconductor Dice, and Intermediate Products Made While Forming at Least One Blind Hole in a Substrate
Programming a Memory Device to Increase Data Reliability
Dynamic Slc/Mlc Blocks Allocations for Non-Volatile Memory
Through-Wafer Interconnects for Photoimager and Memory Wafers
Selective Error Control Coding in Memory Devices
Application:
13/963,636 →
Publication:
US 2013/0326310
Erasing Physical Memory Blocks of Non-Volatile Memory
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.