Patent Assignment
Reel/Frame 036037/0271
Assignment of Assignor's Interest
Recorded: 2015-06-30
Received: 2015-06-30
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(48)
Memory Circuit for Providing Word Line Redundancy in a Memory Sector
Application:
10/635,974 →
Polymer Memory Device Formed in via Opening
Application:
10/614,397 →
Structure and Method for Preventing Uv Radiation Damage and Increasing Data Retention in Memory Cells
Application:
10/460,279 →
Nonvolatile Semiconductor Storage Device and Data Erasing Method
Application:
10/454,630 →
Non-Volatile Memory Read Circuit with End of Life Simulation
Application:
10/431,320 →
Method for Reducing Short Channel Effects in Memory Cells and Related Structure
Application:
10/429,150 →
Method of Programming a Dual Cell Memory Device
Application:
10/422,489 →
Method of Programming and Reading a Dual Cell Memory Device
Application:
10/422,276 →
Method of Dual Cell Memory Device Operation for Improved End-of-Life Read Margin
Application:
10/422,092 →
Amplification Circuit and Optical Communication Apparatus Provided with the Amplification Circuit
Application:
10/418,174 →
Method and System for Detecting Defective Material Surrounding Flash Memory Cells
Application:
10/384,936 →
Charge-Trapping Memory Arrays Resistant to Damage from Contact Hole Formation
Application:
10/382,726 →
Method of Forming Core and Periphery Gates Including Two Critical Masking Steps to Form a Hard Mask in a Core Region That Includes a Critical Dimension Less Than Achievable at a Resolution Limit of Lithography
Application:
10/382,744 →
Method of Programming a Memory Cell
Application:
10/379,885 →
Semiconductor Memory and Output Signal Control Method and Circuit in Semiconductor Memory
Application:
10/360,731 →
Structure and Method for Suppressing Oxide Encroachment in a Floating Gate Memory Cell
Application:
10/364,569 →
Selection Circuit for Accurate Memory Read Operations
Application:
10/361,378 →
Uv-Blocking Layer for Reducing Uv-Induced Charging of Sonos Dual-Bit Flash Memory Devices in Beol Processing
Application:
10/358,589 →
Methods of Controlling Vss Implants on Memory Devices, and System for Performing Same
Application:
10/358,587 →
Non-Volatile Semiconductor Storage Device and Method of Reading Out Data
Application:
10/356,496 →
Method for Reading a Non-Volatile Memory Cell Adjacent to an Inactive Region of a Non-Volatile Memory Cell Array
Application:
10/353,558 →
Novel Non-Volatile Memory Cell and Method of Programming for Improved Data Retention
Application:
10/352,658 →
Pulse Width Detection Circuit Filtering the Input Signal and Generating a Binary Signal
Application:
10/327,094 →
Methods of Forming Passive Layers in Organic Memory Cells
Application:
10/313,494 →
Implantation for the Formation of Cux Layer in an Organic Memory Device
Application:
10/314,054 →
Pre-Charge Method for Reading a Non-Volatile Memory Cell
Application:
10/307,749 →
System for Programming a Non-Volatile Memory Cell
Application:
10/307,667 →
Cascode Amplifier Circuit for Producing a Fast, Stable and Accurate Bit Line Voltage
Application:
10/302,672 →
Method for Reading a Non-Volatile Memory Cell
Application:
10/283,590 →
Buffer Driver Circuit for Producing a Fast, Stable, and Accurate Reference Voltage
Application:
10/282,459 →
Nonvolatile Semiconductor Memory and Method for Controlling Programming Voltage of Nonvolatile Semiconductor Memory
Application:
10/259,761 →
Implementing Reference Current Measurement Mode Within Reference Array Programming Mode or Reference Array Erase Mode in a Semiconductor
Application:
10/254,381 →
Memory Wordline Spacer
Application:
10/243,108 →
Method for Manufacturing Non-Volatile Semiconductor Memory and Non-Volatile Semiconductor Memory Manufactured Thereby
Application:
10/237,805 →
Precharging Scheme for Reading a Memory Cell
Application:
10/226,912 →
Method for Semiconductor Wafer Planarization by Cmp Stop Layer Formation
Application:
10/190,397 →
Process to Improve the Vss Line Formation for High Density Flash Memory and Related Structure Associated Therewith
Application:
10/179,723 →
Test Structure to Measure Interlayer Dielectric Effects and Breakdown and Detect Metal Defects in Flash Memories
Application:
10/174,734 →
Method for Reducing Shallow Trench Isolation Edge Thinning on Tunnel Oxides Using Partial Nitride Strip and Small Bird's Beak Formation for High Performance Flash Memory Devices
Application:
10/126,840 →
Method of Detecting Shallow Trench Isolation Corner Thinning by Electrical Trapping
Application:
10/113,259 →
Low Column Leakage Flash Memory Array
Application:
10/095,739 →
System for Setting Memory Voltage Threshold
Application:
10/096,338 →
Logic Circuit for Fast Carry/Borrow
Application:
10/073,132 →
Diode Fabrication for Esd/Eos Protection
Application:
10/050,394 →
Differential Signal Output Apparatus, Semiconductor Integrated Circuit Apparatus Having the Differential Signal Output Apparatus, and Differential Signal Transmission System
Application:
09/973,767 →
Resource Locking and Thread Synchronization in a Multiprocessor Environment
Application:
09/912,870 →
Dot-Inversion Data Driver for Liquid Crystal Display Device
Application:
09/824,345 →
Cache System with Limited Number of Tag Memory Accesses
Application:
09/768,348 →