IP Library Assignment 037278/0638
Patent Assignment
Reel/Frame 037278/0638

Merger and Change of Name

Recorded: 2015-12-12 Pages: 11
Assignors
ORACLE USA, INC.
Executed: 2010-02-12
SUN MICROSYSTEMS, INC.
Executed: 2010-02-12
ORACLE AMERICA, INC.
Executed: 2010-02-12
Assignee
ORACLE AMERICA, INC.
500 ORACLE PARKWAY, REDWOOD SHORES, CALIFORNIA, 94065
Covered Properties (100)
System and Method for Automatically Distributing Copies of a Replicated Database in a Computer System
Patent: 6,467,046 →
Application: 08/643,550 →
On-Demand, Multi-Language Business Card Printer
Patent: 6,473,728 →
Application: 08/652,034 →
Method & Apparatus for Identifying and Discarding Junk Electronic Mail
Patent: 6,453,327 →
Application: 08/661,686 →
A Method for Generating Database Server Configuration Documentation
Patent: 6,487,558 →
Application: 08/884,287 →
Method and Apparatus for Dynamic Loading of a Transport Mechanism in a Multipoint Data Delivery System
Patent: 6,446,116 →
Application: 08/884,924 →
Secure and Stateful Electronic Business Transaction System
Patent: 6,463,418 →
Application: 08/914,957 →
Mechanism for Dispatching Packets via a Telecommunications Network
Patent: 6,473,425 →
Application: 08/942,809 →
Method and Appratus for Storing and Copying Data via a First Path and a Second Path Wherein Secon Path Bypasses Mirror Driver
Patent: 6,477,591 →
Application: 09/033,806 →
Apparatus and Method for Dynamically Verifying Information in a Distributed System
Patent: 6,466,947 →
Application: 09/044,932 →
Publication: US 2002/0016790
Method and Apparatus for Transporting Behavior in an Event-Based Distributed System
Patent: 6,463,446 →
Application: 09/044,933 →
Methods and Apparatus for Remote Method Invocation
Patent: 6,487,607 →
Application: 09/044,938 →
Method and Apparatus FoR Detecting Input Directed to a Thread in a Multi-Threaded Process
Patent: 6,457,064 →
Application: 09/067,546 →
Method, Apparatus & Computer Program Product for Dynamic Administration, Management and Monitoring of Daemon Processes
Patent: 6,457,063 →
Application: 09/070,494 →
Application Computing Environment
Patent: 6,446,109 →
Application: 09/106,868 →
Publication: US 2001/0039565
Utilizing a Program Counter with One or More Data Counters for Executing Instructions
Patent: 6,467,037 →
Application: 09/107,939 →
Multiprocessing Computer System Employing a Cluster Protection Mechanism
Patent: 6,449,700 →
Application: 09/148,735 →
Publication: US 2002/0004886
Method and Apparatus Ofr Delivery of a Bytecode Embedded Within a Transport Stream
Patent: 6,460,086 →
Application: 09/203,551 →
Environment for Creating and Managing Network Management Software Objects
Patent: 6,466,974 →
Application: 09/205,325 →
Method, Apparatus, and Article of Manufacture for Developing and Executing Data Flow Programs
Patent: 6,449,711 →
Application: 09/244,137 →
Graphics System with Programmable Real-Time Alpha Key Generation
Patent: 6,466,206 →
Application: 09/251,844 →
Method and Apparatus for Generating Text Components
Patent: 6,470,364 →
Application: 09/255,654 →
Method and Apparatus for an Extensible Editor
Patent: 6,480,206 →
Application: 09/255,657 →
Publication: US 2002/0133519
Method and System for Data Processing by Proxy
Patent: 6,487,587 →
Application: 09/259,196 →
High Performance Network Interface
Patent: 6,453,360 →
Application: 09/259,765 →
Method and Apparatus for Indicating an Interrupt in a Network Interface
Patent: 6,467,008 →
Application: 09/259,936 →
Method and Apparatus for Dynamic Packet Batching with a High Performance Network Interface
Patent: 6,483,804 →
Application: 09/260,324 →
Method and Apparatus for Data Re-Assembly with a High Performance Network Interface
Patent: 6,480,489 →
Application: 09/260,333 →
Method and Apparatus for Selective Enabling of Addressable Display Elements
Patent: 6,456,281 →
Application: 09/285,487 →
Exclusive Use of Peripheral Devices
Patent: 6,466,982 →
Application: 09/289,796 →
Method and Apparatus for Displaying Data Patterns in Information Systems
Patent: 6,483,515 →
Application: 09/289,798 →
Dynamic Code Motion Optimization and Path Tracing
Patent: 6,487,715 →
Application: 09/293,076 →
System for Facilitating Remote Access to Parallel File System in a Network Using Privilged Kernel Mode and Unpriviliged User Mode to Avoid Processing
Patent: 6,463,465 →
Application: 09/306,967 →
Method and Apparatus for Retroactively Updating a Communication Billing System
Patent: 6,466,660 →
Application: 09/312,307 →
System, Method and Computer Program Product for Searching for, and Retrieving, Profile Attributes Based on Other Target Profile Attributes and Associated Profiles
Patent: 6,470,332 →
Application: 09/314,690 →
Using Tiling to Improve Performance in a Sparse Symmetric Direct Matrix Solver
Patent: 6,470,368 →
Application: 09/316,173 →
Method for Handling Telephone Commands
Patent: 6,473,496 →
Application: 09/321,480 →
System and Method for Protecting Data and Correcting Bit Errors Due to Component Failures
Patent: 6,473,880 →
Application: 09/323,795 →
Digital Data Transmission via Multi-Valued Logic Signals Generated Using Multiple Drive States Each Causing a Different Amount of Current to Flow Through a Termination Resistor
Patent: 6,477,205 →
Application: 09/324,399 →
Method and Apparatus for Providing Finer Marking Granularity for Fields Within Objects
Patent: 6,453,463 →
Application: 09/327,397 →
Using Time Stamps to Improve Efficiency in Marking Fields Within Objects
Patent: 6,460,067 →
Application: 09/327,399 →
Apparatus and Method for Inserting Repeaters into a Complex Integrated Circuit
Patent: 6,463,574 →
Application: 09/329,552 →
Distinguished Name Scoping System for Event Filtering
Patent: 6,484,200 →
Application: 09/330,790 →
Segmenting Compressed Graphics Data for Parallel Decompression and Rendering
Patent: 6,459,429 →
Application: 09/332,827 →
Opcode Numbering for Meta-Data Encoding
Patent: 6,463,521 →
Application: 09/338,875 →
System and Method Facilitating Determination by Router Nodes in a Network of Ranges of Addresses for Which Each Router Node Is Responsible
Patent: 6,473,431 →
Application: 09/346,801 →
Compensation Circuit for Low Phase Offset for Phase-Locked Loops
Patent: 6,462,593 →
Application: 09/359,952 →
Publication: US 2001/0013800
Mechanism for Reordering Transactions in Computer Systems with Snoop-Based Cache Consistency Protocols
Patent: 6,484,240 →
Application: 09/365,159 →
System and Method for Detecting Double-Bit Errors and for Correcting Errors Due to Component Failures
Patent: 6,453,440 →
Application: 09/368,209 →
Merging Single Precision Floating Point Operands
Patent: 6,463,525 →
Application: 09/375,700 →
Reduced-Cost Remembered-Set Processing in a Train-Algorithm-Based Garbage Collector
Patent: 6,449,626 →
Application: 09/377,137 →
Method and Apparatus for Hass Testing of Busses Under Programmable Control
Patent: 6,473,871 →
Application: 09/386,985 →
Measuring Timing Margins in Digital Systems by Varying a Programmable Clock Skew
Patent: 6,477,659 →
Application: 09/389,726 →
Double Precision Floating Point Multiplier Having a 32-Bit Booth-Encoded Array Multiplier
Patent: 6,446,104 →
Application: 09/396,236 →
Method and Apparatus for Speculatively Locking Objects in an Object-Based System
Patent: 6,487,652 →
Application: 09/409,932 →
Graphics System Having a Super-Sampled Sample Buffer with Efficient Storage of Sample Position Information
Patent: 6,483,504 →
Application: 09/413,106 →
Grounding Computer Systems
Patent: 6,452,794 →
Application: 09/415,110 →
Supporting Multi-Dimensional Space-Time Computing Through Object Versioning
Patent: 6,463,526 →
Application: 09/420,335 →
Method and Apparatus for on-Chip Monitoring of Integrated Circuits with a Distributed System
Patent: 6,457,150 →
Application: 09/433,233 →
Device and Method for Performing a Leading Zero Determination on an Operand
Patent: 6,477,552 →
Application: 09/443,225 →
Method for Load Regulation
Patent: 6,466,936 →
Application: 09/444,714 →
Method and Apparatus for User Level Monitor Implementation
Patent: 6,473,820 →
Application: 09/454,234 →
Method and Apparatus for Performing Power Routing in Asic Design
Patent: 6,446,245 →
Application: 09/477,652 →
Hierarchical Coupling Noise Analysis for Submicron Integrated Circuit Designs
Patent: 6,449,753 →
Application: 09/528,667 →
Method and Apparatus for Dynamically Switching a Cache Between Direct-Mapped and 4-Way Set Associativity
Patent: 6,446,168 →
Application: 09/532,995 →
Method of Measuring the Accuracy of Parasitic Capacitance Extraction
Patent: 6,449,754 →
Application: 09/534,280 →
System and Method for Memory Management Using Contiguous Fixed-Size Blocks
Patent: 6,453,403 →
Application: 09/574,967 →
Method and Apparatus for Zooming on Non-Positional Display Attributes
Patent: 6,476,829 →
Application: 09/596,204 →
System and Method for Transposing Wires in a Circuit Design
Patent: 6,480,996 →
Application: 09/610,746 →
Automatic Test Pattern Generation Modeling for Lssd to Interface with Muxscan
Patent: 6,477,684 →
Application: 09/611,734 →
One-Way Hash Functions for Distributed Data Synchronization
Patent: 6,470,329 →
Application: 09/613,642 →
Method for Determining Optimal Configuration for Multinode Bus
Patent: 6,484,293 →
Application: 09/617,519 →
Circuit for Avoiding Contention in One-Hot or One-Cold Multiplexer Designs
Patent: 6,452,423 →
Application: 09/624,514 →
Integrated Circuit Component Temperature Gradient Reducer
Patent: 6,462,410 →
Application: 09/642,184 →
Peripheral Device Storage System
Patent: 6,473,298 →
Application: 09/651,617 →
Simplified Writeback Handling
Patent: 6,477,622 →
Application: 09/670,856 →
Auto-Detection and Auto-Enable of Compact Pci Bus Pull-Ups
Patent: 6,456,139 →
Application: 09/693,585 →
Suppressing Power Bus Bouncing in a Hot Swappable System
Patent: 6,447,309 →
Application: 09/735,116 →
Publication: US 2002/0072259
Cmos-Microprocessor Chip and Package Anti-Resonance Method
Patent: 6,483,341 →
Application: 09/754,564 →
Publication: US 2002/0084836
Cmos-Microprocessor Chip and Package Anti Resonance Method
Patent: 6,456,107 →
Application: 09/754,573 →
Publication: US 2002/0084837
Circuit Board Retaining Assembly and Method for Use
Patent: 6,471,310 →
Application: 09/766,697 →
Publication: US 2002/0096980
Method and Apparatus for Efficient Electronics Positioning and Connection Systems
Patent: 6,473,307 →
Application: 09/784,470 →
Publication: US 2002/0109972
Latch Control Circuit for Crossing Clock Domains
Patent: 6,486,721 →
Application: 09/798,662 →
Publication: US 2002/0121922
Automated Decoupling Capacitor Insertion
Patent: 6,487,702 →
Application: 09/823,710 →
Publication: US 2002/0144217
Method and Apparatus for Latching Data Within a Digital System
Patent: 6,456,136 →
Application: 09/834,772 →
Publication: US 2002/0149410
Secondary Precharge Mechanism for High Speed Multi-Ported Register Files
Patent: 6,466,497 →
Application: 09/838,774 →
Clock Noise Reduction Apparatus
Patent: 6,462,604 →
Application: 09/847,495 →
Distributing Data to Multiple Destinations Within an Asynchronous Circuit
Patent: 6,486,709 →
Application: 09/854,094 →
Publication: US 2002/0039033
Fan Shroud and Method of Securing a Fan
Patent: 6,483,701 →
Application: 09/870,108 →
Method for Engineering the Threshold Voltage of a Device Using Buried Wells
Patent: 6,489,224 →
Application: 09/872,419 →
Low Voltage Latch with Uniform Stack Height
Patent: 6,472,919 →
Application: 09/872,787 →
Efficient Device Debug System
Patent: 6,472,900 →
Application: 09/874,188 →
Breakout Board Using Blind Vias to Eliminate Stubs
Patent: 6,462,570 →
Application: 09/876,002 →
Low Hold Time Statisized Dynamic Flip-Flop
Patent: 6,448,829 →
Application: 09/876,765 →
Light Conduit for a Storage Device Carrier Assembly
Patent: 6,473,300 →
Application: 09/893,093 →
Multi Part Disk Cage Apparatus
Patent: 6,466,449 →
Application: 09/920,509 →
Method for Reducing Supply Noise Near an on-Die Thermal Sensor
Patent: 6,476,663 →
Application: 09/929,151 →
One-Hot Muller C-Elements and Circuits Using One-Hot Muller C-Elements
Patent: 6,486,700 →
Application: 09/938,353 →
Programmable Sample Filtering for Image Rendering
Patent: 6,459,428 →
Application: 09/970,077 →
Publication: US 2002/0101417
Method and Apparatus That Models Neural Transmission to Amplify a Capacitively-Coupled Input Signal
Patent: 6,472,931 →
Application: 09/991,475 →
Improving Integrated Circuit Performance and Reliability Using Angle Measurement for a Patterned Bump Layout on a Power Grid
Patent: 6,473,883 →
Application: 09/997,437 →