IP Library Assignment 040961/0037
Patent Assignment
Reel/Frame 040961/0037

Assignment of Assignor's Interest

Recorded: 2017-01-12 Pages: 6
Assignors
SILLS, SCOTT E.
Executed: 2017-01-12
RAMASWAMY, DURAI VISHAK NIRMAL
Executed: 2017-01-06
Assignee
MICRON TECHNOLOGY, INC.
MS 1-525, 8000 SOUTH FEDERAL WAY, BOISE, IDAHO, 83716
Covered Property (1)
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
Patent: 9,842,839 →
Application: 15/404,995 →
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Supplement No. 3 to Patent Security Agreement Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
Release of Security Interest Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
Release of Security Interest Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →