Patent Assignment
Reel/Frame 055468/0023
Merger and Change of Name
Recorded: 2021-03-02
Pages: 6
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(48)
Test pattern compression for an integrated circuit test environment
Patent:
6,327,687 →
Application:
09/619,985 →
Method and Apparatus for Selectively Compacting Test Responses
Patent:
6,557,129 →
Application:
09/619,988 →
Continuous Application and Decompression of Test Patterns to a Circuit-Under-Test
Patent:
7,493,540 →
Application:
09/620,021 →
Method for synthesizing linear finite state machines
Patent:
6,353,842 →
Application:
09/620,023 →
Phase Shifter with Reduced Linear Dependency
Patent:
6,874,109 →
Application:
09/713,662 →
Decompressor/Prpg for Applying Pseudo-Random and Deterministic Test Patterns
Patent:
6,684,358 →
Application:
09/713,664 →
Method for Providing User Definable Algorithms in Memory Bist
Patent:
6,671,843 →
Application:
09/737,620 →
Correlation of Behavioral Hdl Signals
Integrated Verification and Manufacturability Tool
Interactive Memory Allocation in a Behavioral Synthesis Tool
Patent:
6,611,952 →
Application:
09/839,376 →
System for Intellectual Property Reuse in Integrated Circuit Design
Method of Compensating for Etch Effects in Photolithographic Processing
Hierarchical Presentation Techniques for a Design Tool
Asymmetric Data Path Media Access Controller
Capacitance and Transmission Line Measurements for an Integrated Circuit
Method and Apparatus for Exploring a Multi-Element Design Through User Directed Selective Rendering
Restartable Logic Bist Controller
Scheduling the Concurrent Testing of Multiple Cores Embedded in an Integrated Circuit
Parallel Electronic Design Automation: Distributed Simultaneous Editing
Parallel Electronic Design Automation: Shared Simultaneous Editing
Synthesis Strategies Based on the Appropriate Use of Inductance Effects
Slack Time Analysis Through Latches on a Circuit Design
Contrast Based Resolution Enhancing Technology
Array Transformation in a Behavioral Synthesis Tool.
Matrix Optical Process Correction
Short Edge Management in Rule Based Opc
Causality Based Event Driven Timing Analysis Engine
Space Classification for Resolution Enhancement Techniques
Polymorphic Computational System and Method in Signals Intelligence Analysis
Functional Verification of Logic and Memory Circuits with Multiple Asynchronous Domains
Patent:
7,143,377 →
Application:
10/701,598 →
Selective Promotion for Resolution Enhancement Techniques
Distributed Configuration of Integrated Circuits in an Emulation System
Testing Embedded Memories in an Integrated Circuit
Creating Photolithographic Masks
Protection Boundaries in a Parallel Printed Circuit Board Design Environment
Measure of Analysis Performed in Property Checking
Short Edge Smoothing for Enhanced Scatter Bar Placement
Hierarchical Feature Extraction for Electrical Interaction
Design for Test of Analog Module Systems
Representing Device Layout Using Tree Structure
Mask Creation with Hierarchy Management Using Cover Cells
Latency Adjustment Between Integrated Circuit Chips
Flexible Horizontal Stack Display and Editor
Connectivity-Based Symbol Generation in Wiring Diagrams
Clustering Circuit Paths in Electronic Circuit Design
Spacers for Reducing Crosstalk and Maintaining Clearances
Coherent State Among Multiple Simulation Models in an Eda Simulation Environment
Automating Interactions with Software User Interfaces
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 31, 2001
From: GUTBERLET, PETER P.; WATERS, SIMON J.; BOWYER, BRYAN D.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 012048/0526 →
Assignment of Assignor's Interest
Aug 7, 2001
From: TATE, MICHAEL
To: ALCATEL INTERNETWORKING (PE), INC.
Reel/Frame 012056/0709 →
Assignment of Assignor's Interest
Aug 31, 2001
From: GARNER, ROBERT E.; GARDNER, DAVID N.; JUSSEL, JEFFREY; ELMAN, ANNA
To: FEI COMPANY
Reel/Frame 012132/0245 →
Assignment of Assignor's Interest
Dec 27, 2001
From: SUAYA, ROBERTO; BILLY, SOPHIE H.M.
To: MENTOR GRAPHICS CORP.
Reel/Frame 012394/0628 →
Document Submitted to Correct a Typographical Error in the Assignee's Address. the Original Incorrect Assignment Is Recorded at Reel 12048 Frame 526-531.
Jan 23, 2002
From: GUTBERLET, PETER P.; WATERS, SIMON J.; BOWYER, BRYAN D.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 012515/0392 →
Assignment of Assignor's Interest
Nov 24, 2003
From: ALCATEL INTERNETWORKING (PE), INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 014152/0399 →
Corrective Assignment to Correct the Name of the Assignee Previously Recorded on Reel 012132 Frame 0245. Assignor(S) Hereby Confirms the Name of the Assignee to Be Mentor Graphics Corporation.
Aug 15, 2006
From: GARDNER, DAVID N.; JUSSEL, JEFFREY; ELMAN, ANNA; LING, DAVID
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018111/0583 →
Assignment of Assignor's Interest
Apr 7, 2008
From: SPEEDGATE, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 020762/0784 →