IP Library Assignment 057561/0253
Patent Assignment
Reel/Frame 057561/0253

Assignment of Assignor's Interest

Recorded: 2021-09-22 Pages: 8
Assignors
UPADHYAY, SAGAR
Executed: 2021-08-24
TANKASALA, ARCHANA
Executed: 2021-08-26
MADRASWALA, ALIASGAR S.
Executed: 2021-08-20
RAJWADE, SHANTANU
Executed: 2021-08-21
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BLVD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Dynamic Gate Steps for Last-Level Programming to Improve Write Performance
Application: 17/411,919 →
Publication: US 2023/0061293
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest May 2, 2024
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 067305/0491 →
Assignment of Assignor's Interest Sep 18, 2025
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 072293/0842 →