IP Library Granted Patent US 11,145,603
Granted Patent B2
US 11,145,603 · App. 16/005,387 · Granted Oct 12, 2021

Integrated circuit packaging system with shielding and method of manufacture thereof

Inventors: Byung Joon Han (Singapore, SG); Il Kwon Shim (Singapore, SG); KyoungHee Park (Seoul, KR); Yaojian Lin (Singapore, SG); KyoWang Koo (Incheon-si, KR); In Sang Yoon (Seoul, KR); SeungYong Chai (Incheon, KR); SungWon Cho (Seoul, KR); SungSoo Kim (Seoul, KR); Hun Teak Lee (Seongnam-si, KR); DeokKyung Yang (Incheon, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L23/552H01L21/486H01L21/6835H01L21/6836H01L23/49827H01L23/49838H01L24/97H01L21/561H01L23/3114H01L23/49805H01L23/49816H01L23/49894H01L24/13H01L24/16H01L25/16H01L2221/68327H01L2224/13111H01L2224/16227H01L2224/97H01L2924/141H01L2924/143H01L2924/1434H01L2924/15311H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2924/3025
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Quick Facts
Patent No.
US 11,145,603
App. No.
16/005,387
Filed
Jun 11, 2018
Granted
Oct 12, 2021
Kind
B2
Art Unit
2814
USPC
257/659
Abstract

An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

Claims (32)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a molded package strip on a carrier, the molded package strip having system interconnects and a solder resist layer mounted over a wafer substrate with the wafer substrate coupled to the system interconnects;

forming an interconnect encasing on the system interconnects and the solder resist layer, the interconnect encasing encases the system interconnects;

singulating the molded package strip to form an integrated package assembly by cutting along a saw street of the molded package strip to expose vertical sides of the integrated package assembly; and

applying a conductive conformal shield structure directly on the integrated package assembly and the interconnect encasing.

2. A method of manufacture of an integrated circuit packaging system comprising:

forming a molded package strip on a carrier, the molded package strip having system interconnects and a solder resist layer mounted over a wafer substrate, the wafer substrate coupled to the system interconnects, and the system interconnects and the solder resist layer are both facing away from the molded package strip;

forming an interconnect encasing on the system interconnects and the solder resist layer, the interconnect encasing encases the system interconnects;

singulating the molded package strip to form an integrated package assembly by cutting along a saw street of the molded package strip to expose vertical sides of the integrated package assembly;

transferring the integrated package assembly to a deposition tape, the interconnect encasing positioned directly on the deposition tape; and

applying a conductive conformal shield structure directly on the integrated package assembly and the interconnect encasing.

3. An integrated circuit packaging system comprising:

an integrated package assembly comprising:

a molded package strip having system interconnects and a solder resist layer mounted over a wafer substrate with the wafer substrate coupled to the system interconnects; and

an interconnect encasing on the system interconnects and the solder resist layer, the interconnect encasing encases the system interconnects; and

a conductive conformal shield structure directly on the integrated package assembly, the interconnect encasing, and the vertical sides of the integrated package assembly.

4. The method as claimed in claim 1 further comprising forming plated through holes in the integrated package assembly and exposing the plated through holes at the vertical sides.

5. The method as claimed in claim 1 further comprising:

forming plated through holes in the integrated package assembly;

exposing the plated through holes at the vertical sides; and

electrically connecting the plated though holes to the conductive conformal shield structure between the wafer substrate and the solder resist layer.

6. The method as claimed in claim 1 wherein applying the conductive conformal shield structure includes electrically connecting the conductive conformal shield structure to an internal conductive layer.

7. The method as claimed in claim 2 wherein singulating the integrated package assembly includes forming plated through holes at a saw street and exposing the plated through holes with a singulation saw.

8. The method as claimed in claim 2 wherein applying the conductive conformal shield structure includes forming the conductive conformal shield structure offset from the solder resist layer.

9. The system as claimed in claim 3 further comprising plated through holes in the integrated package assembly exposed at the vertical sides of the integrated package assembly.

10. The system as claimed in claim 3 further comprising plated through holes in the integrated package assembly exposed on the vertical sides of the integrated package assembly and electrically coupled to the conductive conformal shield structure between the wafer substrate and the solder resist layer.

11. The system as claimed in claim 3 further comprising an internal conductive layer electrically connecting the conductive conformal shield structure.

12. The system as claimed in claim 3 wherein the system interconnects and the solder resist layer are both facing away from the molded package strip.

13. The system as claimed in claim 12 further comprising plated through holes having a diameter of at least 5 micrometers (um) at a vertical edge of the integrated package assembly.

14. The system as claimed in claim 12 further comprising plated through holes exposed at a vertical edge of the integrated package assembly.

15. The system as claimed in claim 12 wherein the conductive conformal shield structure is offset from the solder resist layer.

16. The method as claimed in claim 2 wherein singulating an integrated package assembly includes cutting the plated through holes.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CHANGE OF NAME Recorded Jun 2, 2021
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 056530/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2021
From: HAN, BYUNG JOON; SHIM, IL KWON; PARK, KYOUNGHEE; LIN, YAOJIAN; KOO, KYOWANG; YOON, IN SANG; CHAI, SEUNGYONG; CHO, SUNGWON; KIM, SUNGSOO; LEE, HUN TEAK; YANG, DEOKKYUNG
To: STATS CHIPPAC LTD.
Reel/Frame 056404/0332 →
Cited By (1)
US 12,660,543