Adaptive context metadata message for optimized two-chip performance
Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.
1. A storage device, comprising:
a processor;
a memory including a plurality of memory locations;
a controller configured to provide to the processor,
a descriptor associated with a host command, and
a message mapping a type of the descriptor to a first one of the plurality of memory locations, and a different type of another descriptor to a second one of the plurality of memory locations, wherein the message comprises a range count indicating a number of mappings in the message.
2. The storage device of claim 1 , further comprising:
a master chip and a slave chip, wherein the master chip comprises the controller and the slave chip comprises the processor.
3. The storage device of claim 1 , wherein the memory comprises a static random access memory (SRAM), and wherein the plurality of memory locations comprises a plurality of memory segments in the SRAM.
4. The storage device of claim 1 , wherein the message comprises an opcode.
5. The storage device of claim 4 , wherein the opcode corresponds to the type of the descriptor.
6. The storage device of claim 1 , wherein the message maps the type of the descriptor to at least two of the plurality of memory locations, and wherein the message comprises a plurality of indices associated with the at least two of the plurality of memory locations.
7. A storage device, comprising:
a processor;
a memory including a plurality of memory locations; and
a controller configured to provide to the processor a message mapping a type of a descriptor to a first one of the plurality of memory locations, and a different type of another descriptor to a second one of the plurality of memory locations, wherein the message comprises a range count indicating a number of mappings in the message;
wherein the processor is configured to process the descriptor in the first one of the plurality of memory locations based on the message, the descriptor being associated with a host command.
8. The storage device of claim 7 , wherein the descriptor comprises a plurality of fields each indicating information for processing the host command.
9. The storage device of claim 8 , wherein the processor is configured to refrain from identifying the information indicated in at least one of the plurality of fields in response to a determination that the message indicates the first one of the plurality of memory locations.
10. The storage device of claim 8 , wherein the controller is configured to refrain from indicating the information in at least one of the plurality of fields to the processor.
11. The storage device of claim 7 , wherein the message comprises an opcode corresponding to the type of the descriptor and an index associated with the first one of the plurality of memory locations.
12. The storage device of claim 7 , wherein the message maps the type of the descriptor to a range of the plurality of memory locations, and wherein the message comprises a plurality of indices associated with the range of the plurality of memory locations.
13. The storage device of claim 7 , wherein the message maps the type of the descriptor to a first range of the plurality of memory locations, wherein the message further maps the different type of the another descriptor to a second range of the plurality of memory locations.
14. A storage device, comprising:
a processor;
a memory including a plurality of memory locations;
a controller configured to provide to the processor,
a message mapping a type of a descriptor to a first one of the plurality of memory locations, and a different type of another descriptor to a second one of the plurality of memory locations, wherein the message comprises a range count indicating a number of mappings in the message, and
an instruction to store the descriptor in the first one of the plurality of memory locations, the descriptor being associated with a host command.
15. The storage device of claim 14 , wherein the descriptor comprises a field indicating information for processing the host command, and wherein the processor is configured to refrain from identifying the information indicated in the field in response to a determination that the descriptor is stored in the first one of the plurality of memory locations.
16. The storage device of claim 14 , wherein the descriptor comprises a field indicating information for processing a host command, and wherein the controller is configured to refrain from indicating the information in the field to the processor.
17. The storage device of claim 14 , wherein the message comprises an opcode corresponding to the type of the descriptor, and a plurality of indices associated with a range of the plurality of memory locations.
18. The storage device of claim 14 , wherein the controller is configured to provide to the processor the descriptor to be stored in the first one of the plurality of memory locations after providing the message.