Method to reduce boron penetration in a SiGe bipolar device
View Patent ↗The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
1. A method of manufacturing a semiconductor device, comprising:
forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate;
placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region;
forming a protective layer over the polysilicon layer, the protective layer having a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe) deposition, such that SiGe does not form on the protective layer; and
forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
2. The method recited in claim 1 , wherein the protective layer is resistive to a hydrofluoric etch.
3. The method recited in claim 1 , wherein the protective layer comprises oxides, nitrides or combinations thereof.
4. The method recited in claim 1 , wherein the protective layer is a silicon oxynitride stack.
5. The method recited in claim 4 , wherein a first layer of the protective layer is formed by a plasma enhanced chemical vapor deposition process, including flowing N 2 O at a flow rate ranging from about 40 sccm to about 450 sccm, flowing SiH 4 at a flow rate ranging from about 75 sccm to about 175 sccm and flowing an inert carrier gas at a flow rate ranging from about 1500 seem to about 3500 sccm, and at a temperature ranging from about 350° C. to about 450° C. and a pressure ranging from about 3 torr to about 10 torr and wherein the deposition is conducted at a power ranging from about 75 watts to about 200 watts.
6. The method recited in claim 4 , wherein a second layer of the protective layer is formed by a plasma enhanced chemical vapor deposition process, including flowing N 2 O at a flow rate ranging from about 40 sccm to about 450 sccm, flowing SiH 4 at a flow rate ranging from about 75 sccm to about 175 sccm and flowing an inert carrier gas at a flow rate ranging from about 1500 sccm to about 3500 sccm, and at a temperature ranging from about 350° C. to about 450° C. and a pressure ranging from about 3 torr to about 10 torr and wherein the deposition is conducted at a power ranging from about 75 watts to about 200 watts.
7. The method recited in claim 4 , wherein a third layer of the protective layer is formed by a plasma enhanced chemical vapor deposition process, including flowing N 2 O at a flow rate ranging from about 40 sccm to about 450 sccm, flowing SiH 4 at a flow rate ranging from about 75 sccm to about 175 sccm and flowing an inert carrier gas at a flow rate ranging from about 1500 seem to about 3500 sccm, and at a temperature ranging from about 350° C. to about 450° C. and a pressure ranging from about 3 torr to about 10 torr and wherein the deposition is conducted at a power ranging from about 75 watts to about 200 watts.
8. The method recited in claim 1 , wherein the semiconductor device is an integrated circuit and the gate electrodes form a part of non-bipolar transistors and the method further includes forming dielectric layers over the non-bipolar transistors and the bipolar transistors and forming interconnects over and within the dielectric layer to interconnect the bipolar transistors and the non-bipolar transistors.
9. A method of manufacturing a semiconductor device, comprising:
forming gate electrodes in a non-bipolar transistor region and over a semiconductor substrate;
placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over a bipolar transistor region of the semiconductor substrate;
forming a dielectric layer over the polysilicon layer;
forming a protective layer over the polysilicon layer, the protective layer having a weight percent of hydrogen that is less than about 9%, wherein the protective layer is selective to silicon germanium (SiGe) deposition, such that SiGe does not form on the protective layer;
forming a silicon/germanium (Si/Ge) layer over a collector tub and under a portion of the polysilicon layer within the bipolar transistor region;
forming an emitter layer for bipolar transistors in the bipolar transistor region and over the protective layer and the Si/Ge layer;
patterning the dielectric layer, the protective layer and the emitter layer, including removing the protective layer from the non-bipolar transistor region; and
patterning the polysilicon layer.
10. The method recited in claim 9 , wherein the protective layer is resistive to a hydrofluoric clean.
11. The method recited in claim 9 , wherein the protective layer comprises silicon oxynitride.
12. The method recited in claim 11 , wherein:
a first layer of the protective layer is formed by a plasma enhanced chemical vapor deposition process, including flowing N 2 O at a flow rate of 68, flowing SiH 4 at a flow rate of about 125 sccm and flowing an inert carrier gas at a flow rate of about 2500 sccm;
a second layer of the protective layer is formed by a plasma enhanced chemical vapor deposition process, including flowing N 2 O at a flow rate of about 270 sccm, flowing SiH 4 at a flow rate of about 125 sccm and flowing an inert carrier gas at a flow rate of about 2500 sccm; and
a third layer of the protective layer is formed by a plasma enhanced chemical vapor deposition process, including flowing N 2 O at a flow rate of about 350 sccm, flowing SiH 4 at a flow rate of about 125 sccm and flowing an inert carrier gas at a flow rate of about 2500 sccm, and wherein the protective layer is formed at a temperature of about 410° C., a pressure of about 6 torr, and at a power of about 130 watts.
13. The method recited in claim 9 , wherein the semiconductor device is an integrated circuit and the gate electrodes form a part of non-bipolar transistors and the method further includes forming dielectric layers over the non-bipolar transistors and the bipolar transistors and forming interconnects over and within the dielectric layer to interconnect the bipolar transistors and the non-bipolar transistors.