Memory array circuit incorporating multiple array block selection and related method
View Patent ↗Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
1. In an integrated circuit having a memory array comprising a plurality of linearly-arranged array blocks, a method comprising:
simultaneously selecting in a first mode of operation a greater number of array blocks than in a second mode of operation.
2. The method of claim 1 wherein:
the first mode of operation is a write mode;
the second mode of operation is a read mode; and
in both the first and second modes of operations, simultaneously selecting less than all bit lines in each selected array block.
3. The method of claim 2 wherein:
in the write mode, simultaneously selecting two array blocks and writing M bits into each of said selected two array blocks; and
in the read mode, selecting one array block and reading 2*M bits from the selected array block.
4. The method of claim 3 wherein M=32.
5. The method of claim 3 wherein:
said writing M bits into each of said selected two array blocks comprises simultaneously writing M bits into each of said selected two array blocks.
6. The method of claim 3 wherein:
said selected two array blocks in the write mode comprise adjacent array blocks.
7. The method of claim 6 further comprising:
in the write mode, selecting a single word line that is shared by both of said selected two adjacent array blocks.
8. The method of claim 3 wherein:
said writing M bits into each of said selected two array blocks includes coupling each of a first plurality M of bit lines within a first selected array block to a respective bus line of a first M-bit data bus, and coupling each of a second plurality M of bit lines within a second selected array block to a respective bus line of a second M-bit data bus; and
said reading 2*M bits from the selected array block includes coupling each of a third plurality M of bit lines within a third selected array block to a respective bus line of the first M-bit data bus, and coupling each of a fourth plurality M of bit lines within the third selected array block to a respective bus line of the second M-bit data bus.
9. The method of claim 8 wherein:
said writing M bits into each of said selected two array blocks further comprises selecting a single word line that is shared by the first selected array block and the second selected array block; and
the first selected array block and the second selected array block are adjacent array blocks.
10. The method of claim 8 wherein:
the first M-bit data bus spans the plurality of linearly-arranged array blocks; and
the second M-bit data bus spans the plurality of linearly-arranged array blocks.
11. The method of claim 10 wherein M=32.