Circuit for generating hash values
A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file ( 12 ) is initialized to different data values. A function circuit ( 22 ) performs logical operations based on the selected algorithm and provides a data value to a summing circuit ( 30 ) that is summed with mode dependent constant values selected from registers ( 34 and 36 ), round and step dependent data words generated by a register array block ( 32 ) to calculate the hash value for a text message stored in registers ( 100–115 ).
1. An apparatus for selectively processing first and second cryptographic hash algorithms, comprising:
a register file ( 12 ) having at least five registers for storing chaining variables;
a function circuit ( 22 ) receiving first (B), second (C) and third (D) chaining variables and an output that provides a logical data value;
a first multiplexer ( 24 ) having an input coupled to the register file for receiving a fourth (E) chaining variable and an output that provides the fourth chaining variable when the first cryptographic hash algorithm is being processed by the apparatus and a zero value when the second cryptographic hash algorithm is being processed by the apparatus; and
a summing circuit ( 30 ) having a first input coupled to the output of the function circuit for receiving the logical data value, a second input coupled to the output of the first multiplexer, and an output coupled to the register file.
2. The apparatus of claim 1 , further comprising:
a barrel shifter ( 40 ) having an input coupled to the output of the summing circuit;
an adder ( 41 ) having an input coupled to an output of the barrel shifter; and
a second multiplexer ( 42 ) having a first input coupled to the output of the summing circuit and a second input coupled to an output of the adder.
3. The apparatus of claim 2 , further comprising:
a third multiplexer ( 26 ) having a first input coupled to the output of the second multiplexer ( 42 ) and a second input coupled to the register file ( 12 ) for receiving a fifth (A) chaining variable; and
a fourth multiplexer ( 28 ) having a first input coupled to the output of the second multiplexer and a second input coupled to the register file ( 12 ) for receiving the third (D) chaining variable.
4. The apparatus of claim 3 , wherein the second multiplexer and the fourth multiplexer receive a signal that transfers a summed value from the output of the summing circuit to the register file when the message digest hardware accelerator is processing an SHA-1 hash algorithm.
5. The apparatus of claim 3 , wherein the second multiplexer and the third multiplexer receive a signal that transfers a summed value from the output of the barrel shifter to the register file when the message digest hardware accelerator is processing an MD5 hash algorithm.
6. The apparatus of claim 3 , further comprising:
a first shift circuit ( 16 ) having an input coupled to the register file for receiving the first (B) chaining variable; and
a fifth multiplexer ( 14 ) having a first input coupled to an output of the first shift circuit, a second input coupled to the input of the first shift circuit and an output coupled to the register file for providing the second chaining variable.
7. The apparatus of claim 6 , further comprising:
a second shift circuit ( 18 ) having an input coupled to the register file for receiving the fifth (A) chaining variable; and
a sixth multiplexer ( 20 ) having a first input coupled to an output of the second shift circuit, a second input coupled to the input of the second shift circuit and an output coupled to another input of the sunning circuit.
8. A circuit for generating hash values in a first hash mode and a second hash mode, comprising:
a storage circuit ( 34 , 36 );
a register array ( 32 ) having registers for storing a message and an output for providing a round dependent data value (Wt);
a register file ( 12 ) for storing first (B), second (C), third (D), fourth (B) and fifth (A) chaining variables; and
an adder ( 30 ) having a first input coupled for receiving a first set of constant values stored in the storage circuit for the first hash mode and a second set of constant values for the second hash mode, a second input coupled to the output of the register array, a (hiM input coupled for receiving the fifth (A) chaining variable in the second hash mode and a shifted fifth chaining variable in the first hash mode, a fourth input coupled for receiving a logical function in accordance with the first, second and third chaining variables, and a fifth input coupled for receiving the fourth chaining variable in the second hash mode and a zero value in the first hash mode.
9. An apparatus integrated to provide a hash value of a variable length message in accordance with a first algorithm and a second algorithm, comprising:
a register file ( 12 ) having five registers preset to a first group of values for the first algorithm and to a second group of values for the second algorithm, the register file storing first (B), second (C), third (D), fourth (B) and fifth (A) chaining variables;
a function circuit ( 22 ) receiving first, second and third chaining variables and generating, as an output of the function circuit, a first logical data value for the first algorithm and a second logical data value for the second algorithm;
a storage element ( 34 , 36 ) for supplying a first set of constant values for the first algorithm and a second set of constant values for the second algorithm; and
a summing circuit ( 30 ) having a first input coupled to the output of the function circuit ( 22 ) and a second input coupled to the storage element for receiving one of the first and second sets of constant values.
10. The apparatus of claim 9 , further including a register ray ( 32 ) having a decoder circuit ( 120 ) and a plurality of registers for selecting a data word stored in one of the plurality of registers and supplying the data word to an output of the register array when computing the first algorithm.
11. The apparatus of claim 10 , wherein the register array further includes:
an exclusive-OR ( 116 ) coupled for simultaneously receiving first, second, third and fourth data words stored in the plurality of registers and for generating data; and
a rotate block ( 118 ) having an input coupled to an output of the exclusive-OR and supplying a one bit left circular shift of the data generated by the exclusive-OR to one of the registers in the plurality of registers.
12. The apparatus of claim 10 , wherein an output of the register array is supplied from a word wise circular queue when computing the second algorithm.
13. The apparatus of claim 9 , wherein the first algorithm is an MD5 algorithm and the second algorithm is an SHA-1 algorithm.