IP Library › Granted Patent US 6,705,930
Granted Patent Utility
US 6,705,930 · Confirmation No. 3553

SYSTEM AND METHOD FOR POLISHING AND PLANARIZING SEMICONDUCTOR WAFERS USING REDUCED SURFACE AREA POLISHING PADS AND VARIABLE PARTIAL PAD-WAFER OVERLAPPING TECHNIQUES

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 Code Description Pages PDF
2004-01-21 IFEE Issue Fee Payment (PTO-85B) 2 View
2004-01-21 LET. Miscellaneous Incoming Letter 1 View
2004-01-21 DRW Drawings-only black and white line drawings 6 View
2001-01-04 TRNA Transmittal of New Application 1 View
2001-01-04 SPEC Specification 24 View
2001-01-04 CLM Claims 7 View
2001-01-04 ABST Abstract 1 View
2001-01-04 DRW Drawings-only black and white line drawings 8 View
2001-01-04 OATH Oath or Declaration filed 3 View
2001-01-04 LET. Miscellaneous Incoming Letter 1 View
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Quick Facts
Patent No.
US 6,705,930
App. No.
09/754,480
Filed
2001-01-04
Granted
2004-03-16
Pub. No.
US20010012751A1
Art Unit
3723
PTA
-352 days