Granted Patent
Utility
US 6,555,861
· Confirmation No. 6617
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2010-06-24 | SOL.NTC.SUIT |
Report on the filing or determination of an action regarding a patent | 1 | View | |
| 2010-04-29 | SOL.NTC.SUIT |
Report on the filing or determination of an action regarding a patent | 1 | View | |
| 2001-01-22 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-01-22 | SPEC |
Specification | 43 | View | |
| 2001-01-22 | CLM |
Claims | 11 | View | |
| 2001-01-22 | ABST |
Abstract | 1 | View | |
| 2001-01-22 | DRW |
Drawings-only black and white line drawings | 34 | View |
Inventors
Satoru Yamada
Ome, JAPAN
Kiyonori Oyu
Ome, JAPAN
Takafumi Tokunaga
Iruma, JAPAN
Hiroyuki Enomoto
Mitaka, JAPAN
Toshihiro Sekiguchi
Hidaka, JAPAN
Attorneys & Agents of Record
Classification
USPC
257/298
Prosecution
- Examiner
- WOJCIECHOWICZ, EDWARD JOSEPH
- Art Unit
- 2815
- Customer No.
- 20457
- Docket No.
- 501.39446X00
- Confirmation No.
- 6617
Foreign Priority
2000-013476
·
2000-01-21
·
JAPAN
Publication
- Pub. No.
- US20020043680A1
- Pub. Date
- 2002-04-18
Patent Term Adjustment
-105days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-01-22
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Quick Facts
- Patent No.
- US 6,555,861
- App. No.
- 09/765,574
- Filed
- 2001-01-22
- Granted
- 2003-04-29
- Pub. No.
- US20020043680A1
- Examiner
- WOJCIECHOWICZ, EDWARD JOSEPH
- Art Unit
- 2815
- PTA
- -105 days
External Links