IP Library › Granted Patent US 6,440,816
Granted Patent Utility
US 6,440,816 · Confirmation No. 8854

ALIGNMENT MARK FABRICATION PROCESS TO LIMIT ACCUMULATION OF ERRORS IN LEVEL TO LEVEL OVERLAY

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 Code Description Pages PDF
2001-12-31 TRNA Transmittal of New Application 2 View
2001-12-31 DRW Drawings-only black and white line drawings 7 View
2001-12-31 OATH Oath or Declaration filed 8 View
2001-01-30 TRNA Transmittal of New Application 2 View
2001-01-30 SPEC Specification 19 View
2001-01-30 CLM Claims 7 View
2001-01-30 ABST Abstract 1 View
2001-01-30 DRW Drawings-only black and white line drawings 7 View
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Quick Facts
Patent No.
US 6,440,816
App. No.
09/771,621
Filed
2001-01-30
Granted
2002-08-27
Pub. No.
US20020102811A1
Art Unit
2812
PTA
-200 days