Granted Patent
Utility
US 6,564,362
· Confirmation No. 4600
METHOD OF DESIGNING A LAYOUT OF AN LSI CHIP, AND A COMPUTER PRODUCT
|
⬇ PDF
|
Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-02-22 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-02-22 | SPEC |
Specification | 23 | View | |
| 2001-02-22 | CLM |
Claims | 5 | View | |
| 2001-02-22 | ABST |
Abstract | 1 | View | |
| 2001-02-22 | DRW |
Drawings-only black and white line drawings | 13 | View | |
| 2001-02-22 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Seiko Osaki
Kawasaki, JAPAN
Koji Abe
Kawasaki, JAPAN
Attorneys & Agents of Record
Classification
USPC
716/10
Prosecution
- Examiner
- LIN, SUN J
- Art Unit
- 2825
- Customer No.
- 21171
- Docket No.
- 1448.1011
- Confirmation No.
- 4600
Foreign Priority
2000-202479
·
2000-07-04
·
JAPAN
Publication
- Pub. No.
- US20020004929A1
- Pub. Date
- 2002-01-10
Patent Term Adjustment
-105days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-04-27
CHANGE OF NAME
Recorded 2010-07-27
from
FUJITSU LIMITED
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2008-12-10
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
- Patent No.
- US 6,564,362
- App. No.
- 09/789,490
- Filed
- 2001-02-22
- Granted
- 2003-05-13
- Pub. No.
- US20020004929A1
- Examiner
- LIN, SUN J
- Art Unit
- 2825
- PTA
- -105 days
External Links