IP Library Granted Patent US 6,889,429
Granted Patent B2
US 6,889,429 · App. 09/817,330 · Granted May 10, 2005

Method of making a lead-free integrated circuit package

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,889,429
App. No.
09/817,330
Granted
May 10, 2005
Kind
B2
Abstract

An integrated circuit package ( 60 ) has a substrate ( 12 ) with a first surface ( 51 ) for mounting a semiconductor die ( 20 ) and a second surface ( 52 ) defining a via ( 70 ). A lead ( 26 ) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

Claims (24)

1. A method of making an integrated circuit, comprising the step of plating a conductive material to project outwardly from a second surface of a substrate to form a lead-free first lead of the integrated circuit, wherein the lead-free first lead projects outwardly a distance from the second surface between about 50 microns to about 125 microns.

2. The method of claim 1 , further comprising the step of mounting a semiconductor die to a first surface of the substrate.

3. The method of claim 2 , further comprising the step of forming a signal path on the first surface with the conductive material.

4. The method of claim 3 , further comprising the step of disposing the conductive material in a via defined by the substrate to extend the signal path from the first surface to the second surface of the substrate.

5. The method of claim 4 , further comprising the step of disposing the conductive material on the second surface to extend the signal path from the via to the load-free first load.

6. The method of claim 3 , further comprising the step of wire bonding the signal path to a node of the semiconductor die to couple a signal between the node and the lead-free first lead.

7. The method of claim 1 , further comprising the step of forming an access pad on the second surface, wherein the access pad comprises the conductive material, and wherein the step of plating the conductive material includes plating the conductive material onto the access pad.

8. The method of claim 7 further comprising the steps of;

disposing a photoresist layer on the second surface;

patterning the photoresist layer to expose the access pad; and

plating the conductive material on the access pad.

9. The method of claim 8 , wherein the step of disposing the photoresist layer includes disposing a photoresist layer having a thickness determined by a desired height of the lead-free first lead.

10. The method of claim 1 , wherein the step of plating includes the step of plating copper.

11. The method of claim 1 , further comprising the step of forming a solder mask on the second surface between the lead-free first lead and a lead-free second lead of the integrated circuit.

12. The method of claim 11 , wherein the step of forming includes the step of forming the solder mask after the step of plating.

13. The method of claim 1 , wherein the step of plating includes the step of plating the conductive material in an outward direction for routing a current (I SIGNAL ) through the lead-free first lead that flows parallel to the outward direction.

14. A method of forming an integrated circuit, comprising the steps of:

providing a substrate having a first surface for mounting a semiconductor die; and

plating a conductive material to extend outwardly from a second surface of the substrate to form a lead-free lead of the integrated circuit, wherein the lead-free lead extends outwardly from the second surface a distance between about 50 microns and about 125 microns.

15. The method of claim 14 , wherein the step of plating includes plating copper to form the lead-free lead.

16. A method of making an integrated circuit, comprising the steps of:

mounting a semiconductor die to a first surface of a substrate;

disposing a conductive material along the first surface and through a via of the substrate to form a signal path of the integrated circuit between the first and a second surface of the substrate; and

plating the conductive material on the second surface to form a lead-free lead of the integrated circuit that is electrically coupled to the signal path, and that projects outwardly from the second surface a distance between about microns and about 125 microns.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
RELEASE OF SECURITY INTEREST Recorded Apr 27, 2016
From: WELLS FARGO BANK MINNESOTA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038543/0039 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →