Granted Patent
Utility
US 6,610,573
· Confirmation No. 8456
METHOD FOR FORMING A SINGLE WIRING LEVEL FOR TRANSISTORS WITH PLANAR AND VERTICAL GATES ON THE SAME SUBSTRATE
Inventor:
Rolf Weis
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-06-22 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-06-22 | SPEC |
Specification | 17 | View | |
| 2001-06-22 | CLM |
Claims | 7 | View | |
| 2001-06-22 | ABST |
Abstract | 1 | View | |
| 2001-06-22 | DRW |
Drawings-only black and white line drawings | 6 | View | |
| 2001-06-22 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Rolf Weis
Wappinger Falls, NY
Attorneys & Agents of Record
Classification
USPC
438/268
H10B12/0383
H10W20/092
H10B12/05
H10B12/053
H10B12/09
H10D62/307
H10P30/204
H10P30/208
H10P95/064
H10P95/062
Prosecution
- Examiner
- COLEMAN, WILLIAM D
- Art Unit
- 2823
- Docket No.
- 01 P 11026 US
- Confirmation No.
- 8456
Publication
- Pub. No.
- US20020197801A1
- Pub. Date
- 2002-12-26
Patent Term Adjustment
-8days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-10-07
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-06-06
from
WEIS, ROLF
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-06-22
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Quick Facts
- Patent No.
- US 6,610,573
- App. No.
- 09/888,193
- Filed
- 2001-06-22
- Granted
- 2003-08-26
- Pub. No.
- US20020197801A1
- Examiner
- COLEMAN, WILLIAM D
- Art Unit
- 2823
- PTA
- -8 days
External Links