Granted Patent
Utility
PCT National Stage
US 6,562,695
· Confirmation No. 4518
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING INVOLVING THE SCALE-DOWN WIDTH OF SHALLOW GROOVE ISOLATION USING ROUND PROCESSING
Patented Case
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Inventors
Norio Suzuki
Mito, JAPAN
Hiroyuki Ichizoe
Mizuho, JAPAN
Masayuki Kojima
Kokubunji, JAPAN
Keiji Okamoto
Higashiyamato, JAPAN
Shinichi Horibe
Hachiouji, JAPAN
Kozo Watanabe
Kokubunji, JAPAN
Yasuko Yoshida
Sayama, JAPAN
Shuji Ikeda
Koganei, JAPAN
Akira Takamatsu
Hamura, JAPAN
Norio Ishitsuka
Chiyoda, JAPAN
Atsushi Ogishima
Tachikawa, JAPAN
Maki Shimoda
Hachiouji, JAPAN
Attorneys & Agents of Record
Classification
USPC
438/424
H10B12/00
H10W10/0143
H10W10/17
H10B12/033
H10D1/716
H10D1/042
H10W10/014
H10W10/0145
Prosecution
- Examiner
- OWENS, BETH E
- Art Unit
- 2824
- Docket No.
- 501.40143X00
- Confirmation No.
- 4518
Foreign Priority
11/55529
·
1999-03-03
·
JAPAN
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2006-12-08
from
ISHITSUKA, NORIO,
OKAMOTO, KEIJI,
SHIMODA, MAKI,
SUZUKI, NORIO,
WATANABE, KOZO,
YOSHIDA, YASUKO,
TAKAMATSU, AKIRA,
IKEDA, SHUJI,
HORIBE, SHINICHI,
ICHIZOE, HIROYUKI,
OGISHIMA, ATSUSHI,
KOJIMA, MASAYUKI
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-07-10
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Quick Facts
- Patent No.
- US 6,562,695
- App. No.
- 09/889,018
- Filed
- 2001-07-10
- Granted
- 2003-05-13
- Examiner
- OWENS, BETH E
- Art Unit
- 2824
- PTA
- 0 days
External Links