IP Library Granted Patent US 6,844,236
Granted Patent B2
US 6,844,236 · App. 09/911,364 · Granted Jan 18, 2005

Method and structure for DC and RF shielding of integrated circuits

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Quick Facts
Patent No.
US 6,844,236
App. No.
09/911,364
Granted
Jan 18, 2005
Kind
B2
Abstract

A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate. After bonding, the substructure may be separated from the remainder of the second substrate by propagating a crack along the boundary of the impurity region which separates the substructure from the remainder of the second semiconductor substrate. The method further includes forming the conductive cover over the isolated silicon island or islands by forming insulating layers over the silicon islands then forming a conductive cover layer and conductive sidewalls to surround the silicon island or islands being enclosed.

Claims (27)

1. A method for forming a semiconductor product, comprising:

providing a semiconductor substrate having an insulating layer formed thereover and including a top surface;

providing a substructure having a bottom portion formed of a dielectric film;

bonding said bottom portion of said substructure to said top surface of said substrate;

forming isolated silicon sections, each bonded subjacently by horizontal sections of a conductive material and laterally by vertical sections of said conductive material, in a top portion of said substructure; and

enclosing a group of the isolated silicon sections with additional conductive material.

2. The method as in claim 1 in which said enclosing includes forming insulating materials over said group of isolated silicon sections, forming a conductive cover layer over said insulating materials and forming side conductive materials extending from said conductive cover layer to said vertical sections which peripherally surround said group.

said conductive cover layer and said side conductive materials combining to electromagnetically shield said group.

3. The method as in claim 1 in which said enclosing includes, for each isolated silicon section being enclosed, forming insulating materials over said isolated silicon section, forming a conductive cover layer over said insulating materials and forming side conductive materials extending from said conductive cover layer to said vertical sections which bound said isolated silicon section;

said conductive materials, said conductive cover layer and said side conductive materials combining to electromagnetically shield said isolated silicon section.

4. The method as in claim 3 , in which said forming insulating materials includes, for each isolated silicon section being enclosed, forming a succession of insulating layers and forming trenches in each of said succession of insulating layers, said trenches extending along the periphery of said isolated silicon section, and filling said trenches with said side conductive materials.

5. The method as in claim 3 , in which said horizontal sections of conductive material, said vertical sections of said conductive material, said conductive cover layer and said side conductive materials are each formed of tungsten.

6. The method as in claim 3 , in which said forming insulating materials includes, for each isolated silicon section being enclosed, fanning a succession of insulating layers and said enclosing includes forming one of a continuous opening and a linear array of spaced openings in each of said succession of insulating layers above said vertical sections which bound said isolated silicon section, and filling said formed corresponding openings with said side conductive materials.

7. The method as in claim 1 , in which said providing a substructure includes providing a further substrate having said substructure formed as a portion thereof and further comprising separating said substructure from other portions of said further substrate.

8. The method as in claim 7 , in which said separating takes place after said bonding.

9. The method of claim 7 , in which said separating comprises one of backgrinding and etching.

10. The method as in claim 7 , in which said providing a substructure includes providing said further substrate having a top surface, implanting hydrogen into an upper region of said further substrate, said upper region including a subjacent boundary, fanning trenches within maid upper region and extending vertically downward from said top surface, forming said conductive material over said top surface and filling said trenches, and forming said dielectric film over said conductive material thereby forming said substructure in overturned position as a top portion of said further substrate and,

said separating includes separating said substructure from other portions of said further substrate along a crack propagated along said subjacent boundary.

11. The method as in claim 10 in which said separating includes heating to a temperature within the range of 400° C. to 600° C.

12. The method as in claim 10 , further comprising planarizing after said forming said conductive material over said top surface of said further substrate and filling said trenches, and prior to said forming said dielectric film.

13. The method as in claim 1 , in which said bonding comprises hydrophilic bonding.

14. The method as in claim 1 , wherein said vertical sections of said conductive material and said horizontal sections of said conductive material each comprise tungsten.

15. The method as in claim 1 , wherein said insulating layer comprises a silicon dioxide layer and said dielectric film comprises a silicon dioxide film and said bonding includes hydrophilic bonding.

16. The method as in claim 2 , in which said side conductive materials are not continuous and include openings that extend through said side conductive materials, and further comprising forming interconnect leads extending through said openings.

17. The method as in claim 3 , in which said side conductive materials are not continuous and include openings that extend through said side conductive materials, and further comprising forming interconnect loads extending through said openings.

18. The method as in claim 7 , in which providing said substructure includes providing said substructure including silicon formed over said horizontal sections of said conductive material and over said vertical sections of said conductive material, and

said forming isolated silicon sections including polishing to produce isolated silicon sections.

Assignments (8)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →