Granted Patent
Utility
US 6,614,254
· Confirmation No. 2778
METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EQUIPPED WITH POWER MAKE-UP CIRCUIT USED IN BURN-IN TEST
Inventor:
Satoshi Tamaki
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-06-30 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2001-10-31 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-10-31 | SPEC |
Specification | 21 | View | |
| 2001-10-31 | CLM |
Claims | 7 | View | |
| 2001-10-31 | ABST |
Abstract | 1 | View | |
| 2001-10-31 | DRW |
Drawings-only black and white line drawings | 5 | View | |
| 2001-10-31 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Satoshi Tamaki
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
324/765
G11C29/00
G11C29/50
H10B12/01
H10B12/50
G11C11/401
Prosecution
- Examiner
- TANG, MINH NHUT
- Art Unit
- 2829
- Docket No.
- Q66989
- Confirmation No.
- 2778
Foreign Priority
11-5397 PAT.
·
1999-01-12
·
JAPAN
Publication
- Pub. No.
- US20020027226A1
- Pub. Date
- 2002-03-07
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2006-11-26
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-02-06
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Quick Facts
- Patent No.
- US 6,614,254
- App. No.
- 09/984,843
- Filed
- 2001-10-31
- Granted
- 2003-09-02
- Pub. No.
- US20020027226A1
- Examiner
- TANG, MINH NHUT
- Art Unit
- 2829
- PTA
- 0 days
External Links