Granted Patent B2

US 7,076,014 · App. 10/013,600 · Granted Jul 11, 2006

Abstract

Claims (32)

1. A system comprising a plurality of sub-systems desired to be operated synchronously, each of said plurality of sub-systems comprising:

a divider for dividing a received clock signal and generating a signal including a plurality of clock signal edges, a phase of said signal issued from said divider being adjustable based upon an indirect comparison with a phase of a signal issued from a divider of another of said plurality of sub-systems;

a receiver for receiving a command to be implemented by at least one of said plurality of said sub-systems; and

a control mechanism for implementing said received command at a predetermined one of said plurality of clock signal edges;

wherein a phase measurement of an independent analog input relative to the divider of each sub-system is used to determine a phase difference therebetween.

2. The system as described in claim 1 , wherein a variation of a delay calibration routine is used to determine the relative phase of each divider.

3. The system as described in claim 1 , wherein an adjustment technique based on a gated clock is used to adjust the phase of the divider.

4. The system as described in claim 1 , wherein a series of digitizers and an analog trigger are synchronized.

5. The system as described in claim 4 , wherein a point in time specifically related to the trigger event is determined.

6. The system as described in claim 5 , wherein said system is a digital oscilloscope.

7. The system as described in claim 4 , wherein a decimator is started on a series of digitizer channels in phase.

8. A method for operating a system comprising a plurality of sub-systems synchronously, comprising the steps of:

dividing a received clock signal and generating at each sub-system a signal including a plurality of clock signal edges, a phase of said signal issued from a divider of a first of said plurality of sub-systems being adjustable based upon an indirect comparison with a phase of a signal issued from a divider of another of said plurality of sub-systems;

receiving a command to be implemented by said sub-system; and

implementing said received command at a predetermined one of said plurality of clock signal edges;

wherein a phase measurement of an independent analog input relative to the divider of each sub-system is used to determine a phase difference therebetween.

9. The method as described in claim 8 , wherein a variation of a delay calibration routine is used to determine the relative phase of each divider.

10. The method as described in claim 8 , wherein an adjustment technique based on a gated clock is used to adjust the phase of the divider.

11. The method is as described in claim 10 , wherein an additional adjustment with a fine delay element is used to adjust the phase of the dividers to a fraction of the clock period.

12. The method as described in claim 8 , wherein a series of digitizers and an analog trigger are synchronized.

13. The method as described in claim 12 , wherein a point in time specifically related to the trigger event is determined.

14. The method as described in claim 12 , wherein a decimator is started on a series of digitizer channels in phase.

15. The method as described in claim 8 , wherein said system is a digitized oscilloscope.

16. A method for synchronizing a plurality of sub-systems, comprising the steps of:

measuring a relationship between a divider associated with each of said plurality of sub-systems, wherein a phase measurement of an independent analog input relative to a the divider of each sub-system is used to determine the relationship therebetween;

adjusting a phase of one or more of said dividers to a known relationship with one of said dividers;

issuing a command synchronous to a the divider associated with one of said plurality of sub-systems;

receiving said command at one of said sub-systems; and

acting upon said command synchronous to the divider associated with said one of said sub-system receiving said command.

17. The method of claim 16 , wherein said phase of said one or more of said dividers is adjusted by removing one or more pulses from a clock signal to be forwarded to said sub-system to receive said command so as to retard implementation of said command at said sub-system.

18. The method of claim 17 , wherein said phase is further adjusted with a fine delay to adjust the phase of the dividers to a fraction of the clock period.

19. The system as described in claim 16 , wherein the said system is a digital oscilloscope.

Assignments (8)