IP Library Granted Patent US 6,999,910
Granted Patent B2
US 6,999,910 · App. 10/015,194 · Granted Feb 14, 2006

Method and apparatus for implementing a metamethodology

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,999,910
App. No.
10/015,194
Granted
Feb 14, 2006
Kind
B2
Abstract

The present invention is directed to a comprehensive design flow system. A system and method are provided that provide a comprehensive system to introduce a metamethodology that integrates EDA design tools into a manageable and predictable design flow. A method of designing an integrated circuit may include accessing a design utility operating on an information handling system, displaying a dynamic template on a display device of an information handling system, wherein the dynamic template implements at least two symbols displayable on a display device, in which the at least two symbols each correspond to a respective EDA tool, and arranging the at least two symbols displayed on the display device. The at least two symbols are arranged to indicate an interrelationship of the EDA tools in a design process of an integrated circuit.

Claims (17)

1. A system for designing an integrated circuit, comprising:

a first user computer communicatively coupled to a network, including

a first design navigator, the first design navigator suitable for providing a user interface to enable utilization of EDA tools;

a first project coordinator, the first project coordinator suitable for acting as an administrative interface;

at least two EDA tools, wherein the EDA tools are configured to implement at least one function in a process for designing an integrated circuit (IC); and

a dynamic template, wherein the dynamic template implements at least two symbols displayable on a display device on the user computer, wherein the at least two symbols each correspond to a respective EDA tools accessible by the first design navigator, the symbols arrangeable on the display by a user of the user computer to indicate an interrelationship of the EDA tools in a design process; and

a second user computer communicatively coupled to the network, including

a second design navigator, the second design navigator suitable for providing a user interface to enable utilization of EDA tools;

a second project coordinator, the second project coordinator suitable for acting as an administrative interface;

at least two EDA tools, wherein the EDA tools are configured to implement at least one function in a process for designing an integrated circuit (IC); and

a dynamic template, wherein the dynamic template implements at least two symbols displayable on a display device on the user computer, wherein the at least two symbols each correspond to a respective EDA tools accessible by the second design navigator, the symbols arrangeable on the display by a user of the user computer to indicate an interrelationship of the EDA tools in a design process.

2. The system as described in claim 1 , wherein the interrelationship of the symbols of the dynamic template is a flow.

3. The system as described in claim 1 , wherein the project coordinator is suitable for providing at least one of tool-usage logging, access control, load balancing, file backup and security.

4. The system as described in claim 1 , wherein at least one dynamic template includes at least one of a milestone and sign-off.

5. The system as described in claim 1 , wherein each EDA tool is embedded within a wrapper, the wrapper suitable for always indicating to the project coordinator (which, in turn informs the design navigator) of at least one of entry of an EDA tool and either an exit of an EDA tool or a suspension of the EDA tool operation due to a malfunction or other unexpected occurrence.

6. The sysem as described in claim 1 , wherein dynamic load balancing is utilized by at least one of the primary project coordinator and the secondary or server project coordinator(s).

7. The system as described in claim 1 , wherein heuristic feedback is utilized so that utilization of the EDA tools is monitored and utilized to configure future interrelationships on dynamic templates, new requirements for tools and procedures, and algorithmic and implementation enhancements to exiting tools and procedures.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2002
From: KOFORD, JAMES S.; HAMLIN, CHRISTOPHER
To: LSI LOGIC CORPORATION
Reel/Frame 012623/0064 →