IP Library Granted Patent US 7,371,659
Granted Patent B1
US 7,371,659 · App. 10/020,764 · Granted May 13, 2008

Substrate laser marking

Assignee: LSI Logic Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,371,659
App. No.
10/020,764
Granted
May 13, 2008
Kind
B1
Abstract

A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Claims (26)

1. A method for forming a feature in a substrate, where residue within the feature can be easily removed, the method comprising the steps of:

forming an upper sidewall portion of the feature by laser ablation, the upper sidewall portion forming a void in the substrate, where the upper sidewall portion has an upper sidewall angle, and

forming a lower sidewall portion of the feature by laser ablation, the lower sidewall portion forming a void in the substrate, where the lower sidewall portion has a lower sidewall angle,

where the upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion.

2. The method of claim 1 , wherein the upper sidewall angle of the upper sidewall portion is from about thirty degrees to about sixty degrees.

3. The method of claim 1 , wherein the lower sidewall angle of the lower sidewall portion is from about sixty degrees to about ninety degrees.

4. The method of claim 1 , wherein the lower sidewall portion is formed before the upper sidewall portion is formed.

5. The method of claim 1 , wherein the feature comprises a blind bore formed in the substrate.

6. The method of claim 1 , wherein the upper sidewall portion has a depth of between about four microns and about eight microns.

7. The method of claim 1 , wherein the lower sidewall portion has a depth of between about four microns and about eight microns.

8. The method of claim 1 , wherein the feature has a depth of no more than about twelve microns.

9. The method of claim 1 , wherein the substrate comprises silicon.

10. A method for forming indicia elements on a substrate, where the indicia elements have a shape that aids in removal of foreign material from the indicia elements on the substrate, the method comprising the steps of:

forming an upper sidewall portion of the indicia elements by laser ablation, the upper sidewall portion forming a void in the substrate, where the upper sidewall portion has an upper sidewall angle,

forming a lower sidewall portion of the indicia elements by laser ablation, the lower sidewall portion forming a void in the substrate, where the lower sidewall portion has a lower sidewall angle,

where the upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion, and

forming the indicia elements in a pattern to form identifying indicia on the substrate.

11. The method of claim 10 , wherein all of the upper sidewall portions of all of the indicia elements are formed prior to forming any of the lower sidewall portions of any of the indicia elements.

12. The method of claim 10 , wherein all of the lower sidewall portions of all of the indicia elements are formed prior to forming any of the upper sidewall portions of any of the indicia elements.

13. The method of claim 10 , wherein a preceding one of the indicia elements is completely formed prior to forming a seceding one of the indicia elements.

14. The method of claim 10 , wherein:

the upper sidewall angle of the upper sidewall portion is from about thirty degrees to about sixty degrees,

the lower sidewall angle of the lower sidewall portion is from about sixty degrees to about ninety degrees,

the upper sidewall portion has a depth of between about four microns and about eight microns,

the lower sidewall portion has a depth of between about four microns and about eight microns, and

the indicia element is a blind bore formed in the substrate and has a depth of no more than about twelve microns.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CHANGE OF NAME Recorded Dec 18, 2009
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 023668/0707 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2001
From: YAMAMOTO, HARUHIKO; SETO, HIDEAKI; SATO, NOBUYOSHI; KUROKI, KYOKO
To: LSI LOGIC CORPORATION
Reel/Frame 012396/0026 →