IP Library Granted Patent US 6,948,114
Granted Patent B2
US 6,948,114 · App. 10/132,360 · Granted Sep 20, 2005

Multi-resolution Viterbi decoding technique

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,948,114
App. No.
10/132,360
Granted
Sep 20, 2005
Kind
B2
Abstract

A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.

Claims (56)

1. A method for decoding comprising the steps of:

(A) generating a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics;

(B) generating a plurality of second precision state metrics for a selected subset of said first precision state metrics in response to a plurality of second precision branch metrics;

(C) replacing said selected subset of first precision state metrics with said second precision state metrics; and

(D) storing said first precision state metrics and said second precision state metrics.

2. The method according to claim 1 , further comprising the steps of:

generating said first precision branch metrics in response to a plurality of first precision symbols; and

generating said second precision branch metrics in response to a plurality of second precision symbols.

3. The method according to claim 2 , further comprising the steps of:

generating said first precision symbols in response to first precision quantizing a plurality of received symbols; and

generating said second precision symbols in response to second precision quantizing said received symbols.

4. The method according to claim 3 , further comprising the step of storing said second precision symbols for each of a number of columns of said decoder trellis.

5. The method according to claim 1 , further comprising the step of normalizing said second precision branch metrics prior to generating said second precision state metrics in response to a normalization factor.

6. The method according to claim 5 , further comprising the step of storing said normalization factor for each of a number of columns of said decoder trellis.

7. The method according to claim 5 , wherein the step of normalizing comprises the sub-steps of:

generating a difference between a smallest first precision branch metric of said first precision branch metrics and a smallest second precision branch metric of said second precision branch metrics; and

adjusting said second precision branch metrics by said difference.

8. The method according to claim 5 , wherein the step of normalizing comprises the sub-steps of:

generating a plurality of differences between a first subset of said first precision branch metrics and a second subset of said second precision branch metrics;

generating an average difference from said differences; and

adjusting said second precision branch metrics by said average difference.

9. The method according to claim 1 , further comprising the steps of:

determining a path from one of said second precision state metrics back to an earlier first precision state metric;

generating an earlier second precision branch metric leading into said earlier first precision branch metric;

generating an earlier second precision state metric in response to said earlier second precision branch metric; and

replacing said earlier first precision branch metric with said earlier second precision state metric.

10. The method according to claim 9 , further comprising the steps of:

generating a subsequent second precision branch metric from said earlier second precision state metric to a subsequent first precision state metric along said path;

generating a subsequent second precision state metric in response to said subsequent second precision branch metric; and

replacing said subsequent first precision state metric with said subsequent second precision state metric.

11. An apparatus comprising:

a processor circuit configured to (i) generate a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics, (ii) generate a plurality of second precision state metrics for a selected subset of said first precision state metrics in response to a plurality of second precision branch metrics, and (iii) replace said selected subset of first precision state metrics with said second precision state metrics; and

a state metrics memory configured to store said first precision state metrics and said second precision state metrics.

12. The apparatus according to claim 11 , wherein said processor circuit is further configured to:

generate said first precision branch metrics in response to a plurality of first precision symbols; and

generate said second precision branch metrics in response to a plurality of second precision symbols.

13. The apparatus according to claim 12 , further comprising a quantizer circuit configured to (i) generate said first precision symbols in response to first precision quantizing a plurality of received symbols and (ii) generate said second precision symbols in response to second precision quantizing said received symbols.

14. The apparatus according to claim 13 , further comprising a symbol memory configured to store said second precision symbols for each of a number of columns of said decoder trellis.

15. The apparatus according to claim 11 , wherein said processor circuit is further configured to normalize said second precision branch metrics prior to generating said second precision state metrics in response to a normalization factor.

16. The apparatus according to claim 15 , further comprising a normalization memory configured to store said normalization factor for each of a number of columns of said decoder trellis.

17. The apparatus according to claim 15 , wherein normalizing comprises:

generating a difference between a smallest first precision branch metric of said first precision branch metrics and a smallest second precision branch metric of said second precision branch metrics; and

adjusting said second precision branch metrics by said difference.

18. The apparatus according to claim 15 , wherein normalizing comprises:

generating a plurality of differences between a first subset of said first precision branch metrics and a second subset of said second precision branch metrics;

generating an average difference from said differences; and

adjusting said second precision branch metrics by said average difference.

19. The apparatus according to claim 11 , further comprising a path memory configured to determine a path from one of said second precision state metrics back to an earlier first precision state metric, wherein said processor circuit is further configured to:

generate an earlier second precision branch metric leading into said earlier first precision branch metric;

generate an earlier second precision state metric in response to said earlier second precision branch metric; and

replace said earlier first precision branch metric with said earlier second precision state metric in said state metrics memory.

20. An apparatus comprising:

means for generating a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics;

means for generating a plurality of second precision state metrics for a selected subset of said first precision state metrics in response to a plurality of second precision branch metrics;

means for replacing said selected subset of first precision state metrics with said second precision state metrics; and

means for storing said first precision state metrics and said second precision state metrics.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →