IP Library › Granted Patent US 6,810,510
Granted Patent Utility
US 6,810,510 · Confirmation No. 5190

METHOD FOR ELIMINATING FALSE FAILURES SAVED BY REDUNDANT PATHS DURING CIRCUIT AREA ANALYSIS ON AN INTEGRATED CIRCUIT LAYOUT

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2006-08-24 N570 Communication - Re: Power of Attorney (PTOL-308) 2 View
2006-08-14 PA.. Power of Attorney 5 View
2004-09-20 IFEE Issue Fee Payment (PTO-85B) 2 View
2004-09-20 LET. Miscellaneous Incoming Letter 1 View
2004-07-02 LET. Miscellaneous Incoming Letter 1 View
2004-06-29 NOA Notice of Allowance and Fees Due (PTOL-85) 3 View
2004-06-29 NOA Notice of Allowance and Fees Due (PTOL-85) 5 View
2004-06-29 1449 List of References cited by applicant and considered by examiner 1 View
2004-06-29 892 List of references cited by examiner 1 View
2004-06-29 IIFW Issue Information including classification, examiner, name, claim, renumbering, etc. 1 View
2004-06-29 FWCLM Index of Claims 1 View
2004-06-29 SRFW Search information including classification, databases and other search related notes 1 View
2004-06-18 SRNT Examiner's search strategy and results 2 View
2003-06-24 IDS Information Disclosure Statement (IDS) Form (SB08) 5 View
2003-05-09 N570 Communication - Re: Power of Attorney (PTOL-308) 2 View
2003-04-28 PA.. Power of Attorney 3 View
2002-06-11 TRNA Transmittal of New Application 5 View
2002-06-11 SPEC Specification 11 View
2002-06-11 CLM Claims 7 View
2002-06-11 ABST Abstract 1 View
2002-06-11 DRW Drawings-only black and white line drawings 6 View
2002-06-11 OATH Oath or Declaration filed 3 View
2002-06-11 WFEE Fee Worksheet (SB06) 1 View
2002-06-11 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
Patent No.
US 6,810,510
App. No.
10/167,113
Filed
2002-06-11
Granted
2004-10-26
Pub. No.
US20030229865A1
Art Unit
2825
PTA
0 days