Patent Assignment
Reel/Frame 017388/0799
Release
Recorded: 2005-12-27
Pages: 7
Assignor
SILICON VALLEY BANK
Executed: 2005-12-09
Assignee
HPL TECHNOLOGIES, INC.
2033 GATEWAY PLACE STE 400, SAN JOSE, CALIFORNIA, 95110
Covered Properties
(11)
Automatic Failure Analysis System
Patent:
5,475,695 →
Application:
08/033,775 →
Recipe Editor for Editing and Creating Process Recipes with Parameter-Level Semiconductor-Manufacturing Equipment
Patent:
6,415,193 →
Application:
09/350,039 →
Method for Identifying the Cause of Yield Loss in Integrated Circuit Manufacture
Patent:
6,701,477 →
Application:
09/591,603 →
Method for Selecting an Optimal Level of Redundancy in the Design of Memories
Patent:
6,745,370 →
Application:
09/616,806 →
Recipe Editor for Editing and Creating Process Recipes with Parameter-Level Security for Various Kinds of Semiconductor-Manufacturing Equipment
Correction of Overlay Offset Between Inspection Layers in Integrated Circuits
Correction of Overlay Offset Between Inspection Layers
Method for Avoiding False Failures Attributable to Dummy Interconnects During Defect Analysis of an Integrated Circuit Design
Method for Eliminating False Failures Saved by Redundant Paths During Circuit Area Analysis on an Integrated Circuit Layout
One-Time-Programmable Bit Cell with Latch Circuit Having Selectively Programmable Floating Gate Transistors
Low Standby Current Power-on Reset Circuit
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.