Patent Assignment
Reel/Frame 017325/0435
Assignment of Assignor's Interest
Recorded: 2006-03-10
Pages: 7
Assignor
HPL TECHNOLOGIES, INC.
Executed: 2006-03-02
Assignee
SYNOPSYS, INC.
700 E. MIDDLEFIELD RD., MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(20)
Automatic Failure Analysis System
Patent:
5,475,695 →
Application:
08/033,775 →
Method for Using Wafer Navigation to Reduce Testing Times of Integrated Circuit Wafers
Patent:
6,154,714 →
Application:
08/971,424 →
Method for Using Inspection Data for Improving Throughput of Stepper Operations in Manufacturing of Integrated Circuits
Patent:
6,096,093 →
Application:
08/985,624 →
Recipe Editor for Editing and Creating Process Recipes with Parameter-Level Semiconductor-Manufacturing Equipment
Patent:
6,415,193 →
Application:
09/350,039 →
Method for Identifying the Cause of Yield Loss in Integrated Circuit Manufacture
Patent:
6,701,477 →
Application:
09/591,603 →
Method for Selecting an Optimal Level of Redundancy in the Design of Memories
Patent:
6,745,370 →
Application:
09/616,806 →
Method of providing yield management services employing the internet
Application:
09/631,604 →
Recipe Editor for Editing and Creating Process Recipes with Parameter-Level Security for Various Kinds of Semiconductor-Manufacturing Equipment
Correction of Overlay Offset Between Inspection Layers in Integrated Circuits
Software Development Tool Employing Workflows for Developing User Interactive Programs
Automatic Generation of Join Graphs for Relational Database Queries
Dynamic Database Management System and Method
Correction of Overlay Offset Between Inspection Layers
Method and Apparatus for Determining Fault Sources for Device Failures
Method for reducing data storage requirements for defects identified on semiconductor wafers
Application:
10/124,787 →
Publication:
US 2003/0198375
Method for Avoiding False Failures Attributable to Dummy Interconnects During Defect Analysis of an Integrated Circuit Design
Method for Eliminating False Failures Saved by Redundant Paths During Circuit Area Analysis on an Integrated Circuit Layout
One-Time-Programmable Bit Cell with Latch Circuit Having Selectively Programmable Floating Gate Transistors
Low Standby Current Power-on Reset Circuit
Method and Apparatus for Detection of Failures in a Wafer Using Transforms and Cluster Signature Analysis
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Jul 21, 2005
From: HPL TECHNOLOGIES, INC.
To: SILICON VALLEY BANK
Reel/Frame 016290/0570 →
Release
Dec 27, 2005
From: SILICON VALLEY BANK
To: HPL TECHNOLOGIES, INC.
Reel/Frame 017388/0799 →
Assignment of Assignor's Interest
Jan 11, 2006
From: MARUTYAN, RAFIK
To: HPL TECHNOLOGIES, INC.
Reel/Frame 017474/0757 →