On chip network with memory device address decoding
A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.
1. A network system that enables communication among a plurality of processing elements, comprising:
a network for transferring packets between a plurality of ports, each port conforming to a consistent port interface protocol;
a processing element, comprising:
a bus; and
a memory device, coupled to the bus, that is programmed with addresses of each of the plurality of ports, wherein the memory device provides a destination port address on the bus for a transaction on the bus indicating another port; and
a bus gasket, coupled to the bus and to a corresponding one of the plurality of ports, including a bus interface that generates a packet from the transaction on the bus and a port interface that sends the packets according to the consistent port interface protocol to the port indicated by the destination port address.
2. The network system of claim 1 , wherein the memory device comprises a memory management unit (MMU) that is programmed with the port addresses.
3. The network system of claim 1 , wherein the memory device comprises a direct memory access (DMA) device that is programmed with the port addresses.
4. The network system of claim 3 , wherein the DMA device includes control registers that are programmed with the port addresses.
5. The network system of claim 1 , wherein:
each port including an arbitration interface and a data interface: and
wherein the network comprises:
an interconnect, coupled to the data interface of each of the plurality of ports, that has a predetermined datum width and that includes selectable data paths between any two ports for transferring datums;
wherein each packet comprises one or more datums; and
an arbiter, coupled to the interconnect and to each port, that arbitrates among transaction requests from bus gaskets and that provides acknowledgements via the arbitration interfaces, and that controls the interconnect to enable a data path from a source port to a destination port for each acknowledged transaction.
6. The network system of claim 5 , wherein the port interface submits transactions requests to the arbiter via the arbitration interface, and wherein each transaction request includes the destination port address and a packet size indicative of the number of datums of a packet.
7. The network system of claim 6 , further comprising:
the arbiter further providing data enable signals to a destination port data interface as packet datums arrive; and
the port interface configured to provide datums of a packet via the data interface upon receiving an acknowledgement for that packet, and to receive datums from the data interface upon receiving a data enable signal from the arbiter via the data interface.
8. The network system of claim 7 , wherein the data interface of each port includes an end of packet (EOP) sideband signal that is asserted by a source port bus gasket coincident with a last datum of each packet, and wherein each destination port bus gasket receives datums on consecutive clock cycles upon assertion of a data enable signal until an EOP sideband signal is asserted.
9. The network system of claim 7 , wherein a plurality of priority levels are defined, further comprising:
each bus gasket including an input packet buffer coupled to a buffer manager, wherein the buffer manager provides a buffer release signal via a corresponding data interface to increase a number of buffers available in the input packet buffer; and
the arbiter including buffer management logic coupled to a plurality of buffer counters including one buffer counter for each port, wherein the buffer management logic increments a buffer counter associated with a port when a buffer release signal of that port is provided and decrements the buffer counter associated with a port when an acknowledgement is provided to initiate a transaction to that port as destination; and
wherein the buffer management logic of the arbiter maintains an input buffer high water mark for each destination port input packet buffer by reserving at least one input buffer for each higher priority level by not acknowledging a transaction request having a first priority level if the buffer counter of the indicated destination port would not reserve at least one buffer for each defined priority level that is higher than the first priority level if the transaction request with the first priority level was acknowledged.
10. The network system of claim 9 , further comprising:
each bus gasket including a source request queue for enqueing transaction requests; and
wherein each bus gasket maintains a high water mark for its source request queue by reserving at least one buffer for each higher priority level by not enqueing a transaction request having a first priority level if the source request queue would not have at least one buffer for each defined priority level that is higher than the first priority level if the transaction request having a first priority level was enqueued.
11. The network system of claim 10 , wherein each bus gasket supports split transactions in which a response transaction is conducted from a destination port bus gasket in response to a request transaction from a source port bus gasket and in which the response transaction has a higher priority level than the corresponding request transaction.
12. The network system of claim 11 , further comprising:
each bus gasket configured to re-order transaction requests in its source request queue in response to a re-order signal provided from the arbiter via the arbitration interface that identifies a transaction request to be moved to the front of the source request queue; and
the arbiter being configured to re-order transaction requests of a selected source port bus gasket by providing a re-order signal via the arbitration interface that identifies the transaction request to be re-ordered to overcome a deadlock situation by moving a higher priority transaction request in front of a lower priority transaction request that is blocked by a selected destination port or to overcome a head of line blocking situation by moving a newer transaction request in front of an older transaction request that is unable to complete because a selected destination port bus gasket does not have an available input packet buffer for the older transaction request.
13. An integrated circuit (IC), comprising:
an on chip network (OCN) for transferring packets between a plurality of ports;
a plurality of processing elements, each including a bus and a memory device coupled to the bus that is programmed with port addresses, wherein the memory device provides a destination port address on the bus for a transaction on the bus indicating another port; and
a plurality of bus gaskets, each coupled to a corresponding bus and to a corresponding one of the plurality of ports, each including a processor interface that generates a packets for the transaction on the bus and a port interface, coupled to the processor interface, that sends the packets to the other ports using the destination port address.
14. The IC of claim 13 , wherein at least one memory device comprises a memory management unit (MMU) that is programmed with the port addresses.
15. The IC of claim 13 , wherein at least one memory device comprises a direct memory access (DMA) device that is programmed with the port addresses.
16. The IC of claim 15 , wherein each DMA device includes control registers that are programmed with the port addresses.
17. The IC of claim 13 , wherein:
each port includes an arbitration interface and a data interface; and
wherein the OCN comprises:
an interconnect, coupled to the data interface of each of the plurality of ports, that has a predetermined datum width and that includes selectable data paths between any two ports for transferring datums;
wherein each packet comprises one or more datums; and
an arbiter, coupled to the interconnect and to each port, that arbitrates among transaction requests from bus gaskets and that provides acknowledgements via the arbitration interfaces, and that controls the interconnect to enable a data path from a source port to a destination port for each acknowledged transaction.
18. The IC of claim 17 , wherein each port interface submits transactions requests to the arbiter via a corresponding arbitration interface, and wherein each transaction request includes the destination port address and a packet size indicative of the number of datums of a packet.
19. The IC of claim 18 , further comprising:
the arbiter further providing data enable signals to a destination port data interface as packet datums arrive; and
each port interface configured to provide datums of a packet via a data interface upon receiving an acknowledgement for that packet, and to receive datums from the data interface upon receiving a data enable signal from the arbiter via the data interface.
20. The IC of claim 19 , wherein each data interface of each port includes input and output end of packet (EOP) sideband signals, wherein an input EOP sideband signal is asserted by a source port bus gasket coincident with a last datum of each packet, and wherein each destination port bus gasket receives datums on consecutive clock cycles upon assertion of a data enable signal from the arbiter until an output EOP sideband signal is asserted.
21. A method of providing communication between a plurality of processing elements, comprising:
providing a network with a plurality of ports for transferring packets between the plurality of processing elements, wherein each port is associated with a corresponding one of the processing elements and conforms to a consistent port interface protocol;
programming a memory device coupled to a corresponding processing element with addresses of each of the plurality of ports;
the memory device providing a destination port address on a processing element bus during a processing element transaction on the bus indicating another processing element associated with another port identified by the destination port address;
generating, by a bus gasket coupled between the bus and a corresponding port, a packets including one or more datums incorporating information from the processing element transaction for transfer via the network to the port identified by the destination port address;
submitting a transfer request of a packet to the OCN including the destination port address provided from the memory device.
22. The method of claim 21 , wherein said programming a memory device comprises programming a memory management unit (MMU) with port addresses so that the MMU provides the destination port address upon detecting a transaction to another port.
23. The method of claim 21 , wherein said programming a memory device comprises programming a direct memory access (DMA) device with port addresses so that the DMA device provides the destination port address upon detecting a memory access transaction to another port.